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Is there a way to do mdio writes when the core is configured in udp mode?
Here's my core config:
```
# PHY ----------------------------------------------------------------------
phy: Lit…
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@honorpeter Would you please upload your kernel config file as I mentioned before, I think there might be some config about module sig that has not been enable.
_Originally posted by @eleICoto in h…
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In 'Profiling the Application' of section create my first SDAccel program - The SDAccel.ini has been replaced by the xrt.ini file **SDx 2019** ( [https://www.xilinx.com/support/documentation/sw_manual…
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When Ethernet full-duplex communication is performed (especially at high rates - over 1Gb Ethernet), it is noticed that Tx side of communication becomes the dominant one and completely "kills" the Rx …
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I am trying to compile this plugin on Ubuntu RootFS for a Xilinx Zynq UltraScale board; however, no guide for "Making" the content of the repository seems to have been provided and I am currently stu…
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IMAGE SYNC
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I follwed this tutorial under vivado2018.2, and build the vivado hardware successfully, but after that, when I tried to build the sdk by running build-sdk.tcl in VIVADO tcl console, I got an error, sa…
jkwho updated
4 years ago
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https://github.com/Xilinx/Vitis-AI/blob/996459fb96cb077ed2f7e789d515893b1cccbc95/dsa/DPUCAHX8H-XO/xo_release/src/kernel_DPUCAHX8H_1ENGINE.xml#L7
According to PG367, "DPU_AXI_1" is the interface for…
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https://github.com/rpcme/aws-cloud-and-xilinx-workshop/blob/da51668ec702908d0bf59b6a86d8c45afb70100b/edge/script/amazon-freertos-init.sh#L51
This line is restricting the size to be 7.4G or 7.3G; so…
yunqu updated
5 years ago
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Hi all,
I'm currently facing this issue even after installing the required IP for the pynq-z2 FPGA, which is the exact setup detailed by the tutorial. My vivado version, 2020.1, is also capable of …