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**Test case**
```systemverilog
function void f();
for (int i=N; i > 0; i--) begin
end
endfunction
```
**Actual output**
```systemverilog
function void f();
for (int i=N; i > 0; i--) …
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It would be very helpful for adoption if Verible could provide binary releases.
- Verible requires a C++17-compatible compiler to build. In the EDA world, many people run RHEL6 or RHEL7, which does…
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Like this:
```systemverilog
module m;
foo #(
...
) bar (
.a (a),
.aa (aa),
.aaa (aaa)
);
endmodule
```
If a port is abbreviated with just `.aa`, then there is …
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It would be beneficial to allow the linter to output it's messages in a way that is standardized and easy to parse by various tool.
@wallento is working on something similar for verilator, it may b…
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Example files
* https://github.com/steveicarus/ivtest/blob/master/ivltests/comp1000.v
* https://github.com/steveicarus/ivtest/blob/master/ivltests/comp1001.v
To reproduce:
```
wget -O/tmp/c…
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*Please see this issue as a very optional suggestion.*
Currently, the Verible-generated tools are called `verilog_lint`, `verilog_format`, and `verilog_syntax`. These are very generic names and don…
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In the example below, `foo` is assigned before it is declared and is therefore infered as the 'default net type' according to 6.10, even if the eventual type is not the default net type. SV2V picks th…
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I'm going to try building from scratch for now but this ticket is to formally request an Ubuntu build for the [recently released](https://wiki.ubuntu.com/FocalFossa/ReleaseSchedule) 20.04 LTS "Focal F…
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It would be convenient if the Verible style linter supported separate linter files. For instance, in OpenTitan we currently already leverage two linting solutions (including Verilator lint). Adding ye…
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For example, if a file ends with the line:
```
`define THE_ANSWER 42
```
and there is no terminating line-feed, the entire file is discarded by the lexer.