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[The doc of `firrtl.module`](https://circt.llvm.org/docs/Dialects/FIRRTL/#firrtlmodule-circtfirrtlfmoduleop) described only 1 attr `annotations`.
This is what I tried:
```c
#include
#includ…
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### Describe the bug
Neovim 0.9.1 hangs when nvim-treesitter 0.9.0 is enabled, this happens (presumably) after moving/re-creating files for open buffers.
This happens 100% of the time when, for …
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
```scala
import chisel3._
import chisel3.experimental.conversions._
class Example extends RawModule …
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The following FIRRTL compiled to Verilog needs to have an `initial` block that does a reset if reset is asserted. This happens without randomization, but not with:
```
circuit Foo :
module Foo …
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The FIRRTL specification says:
> As with integer types, an analog type can represent a multi-bit signal. When analog signals are not given a concrete width, their widths are inferred according to a…
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**Type of issue**: bug report
**Impact**: no functional change
**Development Phase**: request
**Other information**
For fixed-width `FixedPoint` addition, the frontend calls `ta…
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Don't allow narrowing sink-flow references.
As mentioned/discussed: https://github.com/llvm/circt/pull/4812#discussion_r1134718303 .
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### Describe the bug
just run plugin update then i find it not work anymore. the codeblock still in markdown file.
### To Reproduce
1. `set conceal=2`
2. open a markdown file which have…
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It shows me the version of the crates beside, but when I try to run some commands when I stay on the same line with crate name - it doesn't do anything at all. For example I try to call `lua require('…
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```scala
circuit Foo:
module Bar:
input in: UInt[2]
output out: UInt
wire a: UInt
a