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## Context
* Currently, our modules only support audio ports (inputs and outputs), limitating us in the possible ways to carry informations.
* We have great needs for different ports (envelope, MI…
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## Problem
The Pauli Twirling module `mitiq.pt` is currently difficult to use on a simulated backend. This is because incoherent/coherent noise is usually modeled using additional layers of noise t…
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Dear Bruno,
my congratulations for squeezing a RV32I core into the Icestick !
I read your Verilog files with joy and I wish to share an idea on how to save a few more LUTs for more peripherals: …
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Before 23.1, we should remove the `storage.mvcc.range_tombstones.enabled` setting, to ensure all clusters are always MVCC-compliant.
Jira issue: CRDB-21122
Epic CRDB-20465
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I think it is important that we have a safe haven against AI, and I didn't think the moment would already be here but blockchains IMO are part of the needed defense against AI takeover.
I believe …
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## Issue Summary
Instead of taking an even split of the stored reagents, plumbing will prioritize emptying a single reagent.
## Round ID:
Local on [master](https://github.com/tgstation/tgst…
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As an interested security enthusiast analyzing SSH3, I wanted to raise some questions about certain security assertions made in the documentation, as well as use of the SSH3 name/branding before forma…
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First: I'm excited about the idea of a machine-speed SGP4 implementation that can be called from Python! This will meet an important need for folks finding the pure-Python `sgp4` not fast enough for t…
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When declare (qu)bits, is `bit foo;` equivalent to `bit[1] foo;`? In other words, singleton registers and single bits type-equivalent?
For example, are these valid?
```
def a_subroutine qubit[1]…
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# Circuit as reference state in the ansatz definition
**What problem does this feature request help you overcome?**
In our stack of Ansätze, located in `toolboxes/ansatz_generator`, most of them…