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Author Name: **Alex Solomatnikov**
Original Redmine Issue: 544 from https://www.veripool.org
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Obviously not synthesizable but useful for testbenches and behavioral models.
Example:
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Hi
I am sorry, I have a question about slave mode' reading and writing. when muti-slave write package in same time. because we send socket package which is splitted in two. fristly, writing pac…
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Author Name: **أحمد المحمودي**
Original Redmine Issue: 1494 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
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When building verilator 4.018, the build failed wh…
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Dear cocotb community,
I'm new to cocotb and trying to get the endian_swapper exampl running.
My setup is:
- Win10
- Aldec Active-HDL9.3
- Miniconda with Python 3.7
What I did so far:
1. …
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There is a problem with naming of signals (duplicate of check-axilite-reset):
` m_check_axilite_handshakes("check-axilite-reset", this),`
where it should be renamed to:
`m_check_axilite_hand…
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I am not a contributor on this project, so can't do commits. Here are some the updates that
- restore othervars being available from ModuleDecl. It used to be there and then disappeared.
- updates …
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Currently systemc-clang requires there to be a 'main()' as its starting point for finding module instances. It is often the case that the top-level module declaration is the only one required. There…
rseac updated
4 years ago
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[`https://github.com/black-parrot/black-parrot/blob/master/GETTING_STARTED.md#getting-started-full`](https://github.com/black-parrot/black-parrot/blob/master/GETTING_STARTED.md#getting-started-full)
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Author Name: **Robert Baruch** (@RobertBaruch)
Original Redmine Issue: 1115 from https://www.veripool.org
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I'm using Verilator built from head (11/26/2016), and 1800-2012 SystemVerilog.
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I install AFF3CT by following instructions:
```
git clone --recursive https://github.com/aff3ct/aff3ct.git
mkdir aff3ct/build
cd aff3ct/build
cmake .. -DCMAKE_BUILD_TYPE="Release"
make -j4
```
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