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Failing in all tools that do elaboration (slang, verilator) with errors like:
```
../../../third_party/cores/veer-el2/testbench/uvm/mem/hdl/dccm_monitor.sv:4:28: error: use of undeclared identifier …
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have up…
ftab updated
3 months ago
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It is an enhancement request.
VHDL is supported, but Verilog HDL is not.
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Continuing Issue #661
After force recreating thumbnails for all ETDs, #685, manually create thumbnails of ETDs where the title or cover page is not the first page.
Create thumbnail of page 1:
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Consider that we have a source code file named `test.ll` with the following contents:
```llvm
define ptr @f(i32 %n) {
ret ptr null;
}
declare void @llvm.coro.resume(ptr)
define i32 @main()…
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Hi,@koide3,
When I run " roslaunch hdl_people_tracking hdl_people_tracking.launch ",the following error occurs.
... logging to /home/jintaiyu/.ros/log/9cdcaf3c-f88f-11e8-b306-000ec6a10ce2/roslau…
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Здесь хотим научить (или напомнить) основы синтаксиса `=>` много комментариев на эту тему.
В качестве примера --- сумматор на комбинационной логике.
Стоит написать про "классические" тестбенчи (что…
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We need to test and merge the following forks:
HDL32 https://github.com/smori/loam_velodyne/commit/774d5117ffc7662cd30ef831be9ce82b6985d5df
HDL64 https://github.com/YANG-H/loam_velodyne/commit/ba1d606…
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Although the HDL-generator class is in the working tree, it has never been tested on correct functionality. This is the reason it is not enabled. It is on the todo list and will be enabled as soon as …
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The following gates have to be implemented as internal chips:
### Very basic:
- [x] ~Nand~ (https://github.com/DmitrySoshnikov/hdl-js/commit/4e0b154520cb702ad95db7e45d679ce5cf4bcac1)
- [x] ~Nor…