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The semantics provided for the SDIV instruction trigger undefined behaviour on INT_MIN / -1.
For example, 010cc19a sdiv x1, x0, x1 gives us something like:
```llvm
%4 = load i64, ptr %X0, align 8…
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After sorting out test not included into `spectest.data` (see Raku/roast#657) I ended up with a number of cases where it is uncertain what to do with them. Because most of the doubts are caused by que…
vrurg updated
4 years ago
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Would it be possible to provide an HTML/EPub version of the specification? I have tried translating the specification from its latex sources to HTML with Pandoc, but Pandoc takes a ridiculously long t…
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Apparently on ARM (edit: and riscv) when
* a store is unaligned
* and crosses a page boundary
* and one page faults but the other doesn't
then there is no guarantee that the part of the store …
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It would be nice to support extrapolating to `missing`
```julia
> using Interpolations, Missings
> A = rand(20)
> A_x = collect(1.0:2.0:40.0)
> knots = (A_x,)
> itp = extrapolate(interpolate(k…
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It would be useful to have a class for files (e.g. `File`) and basic functions for creating objects of such classes. I can imagine that this file class is a simple extension of `character`, because t…
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Three options:
* **Wasm spec references JS spec for the memory model**. This is the easiest model to start with. If Wasm needs to express something that's not available in JS, it can explain that in …
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Just to double check: the functions `decode` and `execute` are not keywords in Sail? I'm asking, because I want to know if there is a purely syntactic way of distinguishing the definitions of instruc…
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Hello,
The checkct plugin sometimes erroneously reports control flow leak on arm `clz` instruction, if the operand is secret-dependent.
The decoding produced by `unisim_archisec` has branching, …
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**Is your feature request related to a problem? Please describe.**
I have [an out-of-tree processor module](https://github.com/cyrozap/ghidra-md32) for a CPU whose instruction set has mixed four-byte…