-
I have regenerated the ip cores: "tri_mode_eth_mac_v5_4" and "mac_fifo_axi4" successfully, but it just can not pass the synthesis. The error showed: HDLCompiler:1304 - "C:\Users\tang\Desktop\IPBus_ATL…
-
Hello,
I am using CMake as my build system for RTL simulations.
Very often I have a scenario where I have a custom command that would generate Verilog files.
I am using custom_commands rather tha…
-
When I run it with one of my toplevel files, git gives this. Where is outvTbgenerator.py
$ python /home/local/NDC/ssheikh/.vscode/extensions/truecrab.verilog-testbench-instance-0.0.5/out\vTbgenerat…
-
Currently I have to supply all parameters twice. At first to `Add-AppveyorTest` to create a test and second to `Update-AppveyorTest` to overwrite an existing test with a new status.
It would be nic…
-
According to AXI4 spec, arlock/awlock signals should be of width 1. However, in (as far as I can tell) all sources that contain an AXI port, they are of width 2.
At the action_wrapper level in the …
-
Hi @koide3 ,
I have noticed that the loop closure corrections shift the `map` frame against the `odom` frame. Is this by design? Usually, the `map` frame is static and the corrections from loop closu…
-
Hi @noelpedro,
I have a version of your HDL running on a ZCU102 with an fmcomms2/3 card.
I'm seeing some strange behavior where my correlation results all drop and then re-adjust. This causes t…
-
Hi,
I understand this is a work in progress project, I would like to build 2 to test on a A2000 and A500.
unfortunately I had a denied response for the other project.
I am willing to share the in…
-
Based on https://github.com/cocotb/cocotb/pull/1250 (by @Fatsie) proposals and discussion in https://github.com/cocotb/cocotb/issues/1682
We have discussed a bit internally on https://github.com/co…
-
See https://github.com/hdl/awesome/issues/172#issuecomment-782895784
Added separate issue for now in order to remind me. Will think about how to best add it.
Main worry I have now is that I try to l…