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## Describe the bug
There is a difference in the elaboration of generate blocks between VCS and Slang. VCS can elaborate the following code snippet without issues, but Slang cannot. The code has been…
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Thank you so much for your hard work and dedication to the slang project. Your efforts in developing and maintaining this tool are greatly appreciated by the community. It's thanks to contributors lik…
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**Esercizio 3 (5 punti)**
Descrivere in SystemVerilog un blocco che realizza un contatore modulo 11
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**Esercizio 3 (5 punti)**
Descrivere in SystemVerilog un blocco che realizza un contatore modulo 13
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This is an feedback from @olofk.
![image](https://user-images.githubusercontent.com/2922232/210678769-4edf98e4-7ae4-4011-a459-091fa3413b5f.png)
* FuseSoC
* https://github.com/olofk/fusesoc
…
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I followed the instructions [here](https://github.com/rems-project/sail/blob/sail2/INSTALL.md) and installed sail via opam. However I can't find an `-emacs` flag which supposedly is needed by the sail…
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It seems the current version of verilator doesn't support module like this:
```
module via (.a(w), .b(w));
inout w;
wire w;
endmodule
```
There was a discussion
https://forums.xilinx.com/t5…
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Hi Lawrie and thanks for that great work!
As you mentioned:
> This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but so…
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I'm sure the Kaitai maintainers have noticed that there is a large pocket a Kaitai users, or devs who would be Kaitai users, who are not the original target audience (reverse engineers). These users a…
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# Issue: Develop Testbench Environment for Testing CSI-2 Camera Model in Cocotb
## Description
The goal of this issue is to develop a testbench environment for testing a CSI-2 camera model using…