-
(not sure if this is a duplicate of some existing issue)
Consider something like this
```verilog
typedef enum {
CMD_NO_OP = 0, // Get fifo free slots
CMD_STATUS = 1, // g…
-
Hi,
I see verible supports the project: https://github.com/google/riscv-dv
However, I got error when I run the script: `verilog_style/run.sh`.
The script:
```
find src/ -type f \( -name "*.sv" …
-
Hello @mithro and @eine.
I think that you both know very well the FOSS ecosystem, but I know that you have predilections :P (Verilog and VHDL, of course). Would you check the following categorized …
-
I found the style check crashed due to "type_id::create($sformatf("instr_%0d", i));"
Here is [link](https://github.com/google/riscv-dv/blob/f7e35d7939a27ae17b0481eb070e9a36ea335d1f/src/riscv_instr_…
-
Example formatter output of reduced test case:
```systemverilog
task t;
a_pkg::foo #(x)::func();
endtask
```
Should be:
```systemverilog
task t;
a_pkg::foo#(x)::func();
endtask
``…
-
The following code causes verible to throw an error and stop processing.
```systemverilog
`ifndef uvm_component_new
`define uvm_component_new \
function new (string name="", uvm_component …
-
Try as we may, it is impossible to get all users to agree on style. To reach more users with the style linter, we must accommodate different tastes.
For some lint rules, it makes sense to be able …
-
Reduced test case:
```systemverilog
task S;
`ppgJH3JoxhwyTmZ2dgPiuMQzpRAWiSs(
{xYtxuh6.FIMcVPEWfhtoI2FSe, xYtxuh6.ZVL5XASVGLYz32} == SqRgavM[15:2];
JgQLBG == 4'h0;,
"foo")
endtask
```
cr…
-
Test case:
```systemverilog
constraint classname::constraint_c {
a
-
Just putting down a note here that it would be great if we can eventually add support for Verible, an open-source style linter/formatter (see: https://github.com/google/verible).
I will add some ex…