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@Abhishek-Varma suggested the following command:
```
iree-compile --mlir-elide-elementsattrs-if-larger=2 \
--iree-hal-target-backends=amd-aie \
--iree-amdaie-use-pipeline=pad-pack \
…
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Under Hybrid Target, I have created target specific config or compiler options in the backend(codegen), These option are given with default values too.
Example:
TVM_ROOT/src/relay/backend/contri…
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I tried to build ort on my laptop with VS 2022 according to this guide: [Vitis AI ](https://onnxruntime.ai/docs/build/eps.html#amd-vitis-ai)
But failed and got
```
2024-03-11 17:45:37,213 build […
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Environment:
- Xilinx Alveo U200 Data Center FPGA Acceleration card
- Ubuntu 22.04.4 LTS
- Vitis Unified IDE 2023.2
- gcc version 11.4.0, installed from "sudo apt install build-essential"
- Proje…
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Could this project add Xilinx Virtual Cable Support? JTAG and programming are very solid in this project, found some other XVC project, like https://github.com/kholia/xvcpi and https://github.com/Berk…
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LLVM currently has support for arbitrary bitwidth integers.
https://llvm.org/docs/LangRef.html#integer-type
https://reviews.llvm.org/rG5f0903e9bec97e67bf34d887bcbe9d05790de934
https://reviews.llvm.…
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**Question not an Issue**
Got the installation working on Linux which is great, but I was wondering, what is the scope of what the driver will allow you to do? It seems that most of the software lo…
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I am trying to load and quantize the YOLOv5 model, using the following code:
`device = torch.device('cpu')
model = torch.hub.load('ultralytics/yolov5', 'yolov5n', pretrained=True)
rand_…
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Hi,
I would like to use Xilinx DPU to accelerate RNNs/LSTMs on a ZynqMP Platform, preferably ZCU102 or ZCU104. As far as I know the DPU-TRD dosn't support those layers. But I have found DPU-RNN (ht…
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## 🐛 Bug
Android Apk load llm crash, org.apache.tvm.Base$TVMError: InternalError: Check failed: type_code_ == kTVMObjectHandle (0 vs. 8) : expected Object but got int
## To Reproduce
Steps to…