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Something blocks for 135 ms on occasion in this experiment. Commenting out ```self.pmt.count()``` prevents this blocking.
```
from artiq.experiment import *
import numpy as np
class MasterIsS…
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M-Labs added support for VHDCI control of EEMs. https://github.com/m-labs/artiq/issues/817#issuecomment-406186764
Start with an AMC+RTM system that works on benchtop. Add FMC DIO 32 ch adapter and …
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A fresh issue for one of the two boards proposed in [[RFC] Sinara Servo sinara-hw/meta#16](https://github.com/sinara-hw/meta/issues/16).
This would be a high performance board using the FPGA on a K…
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**Issue by [sbourdeauducq](https://github.com/sbourdeauducq)**
_Sunday Jul 07, 2019 at 02:16 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/136_
----
I'm not sure is this is act…
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Discussing plans for WR with @sbourdeauducq https://freenode.irclog.whitequark.org/m-labs/2019-02-22
Once concern with WR is the possibility of adding noise to the recovered clock when it is routed…
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When bug reporting, it's useful to have an idea what ARTIQ version is causing the issue. I suggest adding a `--version` flag to `artiq_run` or `artiq_master` to print the version number.
It could …
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I cannot get a PLL lock with a new v1.3 Urukul using clk_sel=2 (MMCX), nor with clk_sel=0 (internal XO)
This board is successfully locking using clk_sel=1 and a 125MHz signal applied to the front S…
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# Bug Report
## One-Line Summary
SUServo IIR coefficient read back does not work
### Steps to Reproduce
```python
a1 = -1
profile = 0
addr = 5
base = (self.aom_397_doppler.serv…
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We should have CI tests for
- Python unittests,
- code style (YAPF), and
- Flake8,
and a bot to auto-merge PRs on passing tests.
Any of the usual suspects (Travis, Semaphore, …) will do; t…