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I have a design with matrix of DSPs that is supposed to re-use the DSP cell. I name each with instantiation of the DSP cell using ``setattr`` to make them easy to track down during VCD traces like so:…
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## Observed Behavior
I simulated the simple system example using VCS, following the guide in https://github.com/lowRISC/ibex/blob/master/examples/simple_system/README.md
I build the simulati…
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Following the steps [here](https://github.com/ucb-bar/chisel-tutorial/wiki/the-basics)
At the "Generating Verilog" step when I run `./run-examples.sh GCD --backend-name verilator` command, I get an …
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1. Can you add a TCL command that returns a list of the hierarchy without signals?
2. Can you add the ability to add waveforms via wildcards `*`?
For 1., commercial HDL simulators, they have proce…
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**What would you like to be added**:
Is there a recommended way to stop people from accessing the Rubrik Console via the Rubrik Proxy directly so they will only be able to access Rubrik functiona…
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Hi! Recently I templated latest Ubuntu in vCloud environment.
When I created first dozen VMs, it worked fine. I even wrote a blogpost about my success somwhere.
But now, when I created another d…
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## Observed Behavior
I am trying to build ibex using verilator installed on ubuntu 22.04, verilator version: 4.038 2020-07-11. The build breaks with error point to RV32E is not defines.
## E…
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This issue is a discussion thread and followup about adding Chisel support to TerosHDL extension.
Here I list the initial points I identify as requirement for support:
- Chisel is a DSL based on…
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```
What steps will reproduce the problem?
1. Installed latticist and playwith via the usual package installing tools of R
2. library(latticist)
3.latticist(some.data)
What is the expected output? Wh…
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```
This isn't really an 'issue', but it something for which the syntax is baffling
me. The read groups are assigned as such:
RG='@RG\tID:1\tPL:ILLUMINA\tSM:'$READ_GRP'\tDS:ref='$ASSEMBLY',pfx='$REF…