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Hi - Not really an issue, but I just want to start a discussion. I was wondering if there are any plans to move the linux-kernels/uboot repos to 2020.1? the fpga manage has matured so loading bitstrea…
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You can add the board to ICEStudio but the command line to upload the bitstream based in python is not gonna work because you can not configure the port in Apio, it is fixed.
I can solve the problem …
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More of a question than an issue (I do apologise if this was the wrong forum for this question):
Suppose that my `y` variables are between 0 and 10. Was wondering if there is a way to squash the like…
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The Rust compiler is unlikely to successfully compile anything that requires explosively recursive expressions. Even after https://github.com/rust-lang/rust/pull/122717 for example, it will still have…
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### What feature would you like to see?
I'd like to suggest 2 improvements for binary view mode in hex editor.
1. Little endian bit order in each byte displayed as an option (now it is big endian on…
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### Description
There are some gaps in the config files for the `cw310` interface which goes through the SAM3X.
* Some pin names are not recognised, leading to errors like `Error: Invalid pin na…
jwnrt updated
5 months ago
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Currently when using the bitread tool, the architecture defaults to the 7 series. When a bitstream is given of a different architecture such as Ultra Scale, this is the error messgae:
`Part file no…
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```
The bitstream documentation doesn't exclude the ability to execute a copy of a
buffer to alt ref and a copy of a buffer to golden at the same time.
So if last was copied to alt and alt was copie…
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```
The bitstream documentation doesn't exclude the ability to execute a copy of a
buffer to alt ref and a copy of a buffer to golden at the same time.
So if last was copied to alt and alt was copie…
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Hi,
Should the IF_PTP_PERIOD be set to 6.4 in a fpga_10g design?
If yes, wouldn't it be nice to move this to an input parameter of fpga module and initialize it in config.tcl, so that there would …