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I would like to simulate a RISC-V MCU, for example, SiFive FE310. What are the available options? Possibly, QEMU can be used similar to ARM and Xtensa?
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Fail randomly (probability is around 10%).
```
FAIL: CIRCT :: Conversion/PipelineToHW/test_outlined.mlir (582 of 641)
******************** TEST 'CIRCT :: Conversion/PipelineToHW/test_outlined.mlir'…
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Dear Bruno,
my congratulations for squeezing a RV32I core into the Icestick !
I read your Verilog files with joy and I wish to share an idea on how to save a few more LUTs for more peripherals: …
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Hi There,
The README mention about setting up the following env vars, but riscv-toolchains-rvv-0.8.x and riscv-toolchains-rvv-0.9.x has different directory structures. If I want to use riscv-toolch…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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Reproduction steps:
```sh
$ cat > foo.wake
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Hi, I'm new to the yocto project and trying to build and boot a simple linux distro on qemu emulating the unleashed board.
I followed the readme, cloned bitbake, oe-core and meta-sifive, and ran `k…
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### Environment
Hardware model: Surface Laptop 4 (intel)
Kernel version: Linux surface 6.0.9-surface #1 SMP PREEMPT_DYNAMIC Thu Nov 24 19:45:07 UTC 2022 x86_64 GNU/Linux
CPU: Dual Core Intel Core i…
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I am really interested with this project as I am really new to RISC-V and trying to learn how to implement my own bootloader. May I know is there any step by step or guidance on how to use the boot pr…
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Hi there! I really appreciate your time and your reply. As you could see, I am a beginner of RISC-V and Linux, so please forgive me if I am asking silly questions.
For the last few days, I managed …