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Dear Vitis AI Team,
I am writing to express my appreciation for the comprehensive suite of tools and resources that Vitis AI provides. The integration of optimized IP, tools, libraries, and models …
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Hi all,
For dual-port FPGA boards, is it possible to support bump-in-wire based on the project?
Thanks,
Yang
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update the ml-suite and give a ami
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We have around 25 users logged in with mix at standard resolution and output resolution at 1280x720 at 1024 Kbps Intel MCU 4.2.1 Ubuntu 18.04 GPU Accelerated.
When intel_gpu_top i can see render bu…
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# Prerequisites
Please answer the following questions for yourself before submitting an issue.
- [ ] I am running the latest code. Development is very rapid so there are no tagged versions as of…
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``` r
library(dplyr, warn.conflicts = FALSE)
library(DBI)
Sys.setenv(PGDATABASE = "crsp", PGHOST = "10.101.13.99")
Sys.setenv(PGUSER = "yanzih1", PGPASSWORD = "temp_20190711")
pg %
mutat…