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Reading the commit notes from
https://github.com/facebook/CacheLib/commit/009e89ba2b49b1fbbc48d03c3f81046de28bd6ed
I tried to enable FDP by adding
```
"enableFDP": true,
"navyEnableIo…
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https://github.com/dgraph-io/benchmarks/blob/8ed23af58e6d5f3e4cd1b3ea0517653ce4200ccd/cachebench/ristretto/bench.go#L48
```
flagSuite = flag.String(
"suite",
"all",
`You can chose from the…
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Hi,
I have been exploring using `cachelib` for an experiment, where I am using 1 `cachebench` thread to send requests to an underlying SSD (using `nvmCache`) for a certain `qDepth`. However, despit…
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```
I have implemented a concurrent LIRS cache. It is actually only an
approximation by default, as the cache is segmented (each segment is
synchronized - same as the concurrent hash map), and becau…
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```
I have implemented a concurrent LIRS cache. It is actually only an
approximation by default, as the cache is segmented (each segment is
synchronized - same as the concurrent hash map), and becau…
-
```
I have implemented a concurrent LIRS cache. It is actually only an
approximation by default, as the cache is segmented (each segment is
synchronized - same as the concurrent hash map), and becau…
-
```
I have implemented a concurrent LIRS cache. It is actually only an
approximation by default, as the cache is segmented (each segment is
synchronized - same as the concurrent hash map), and becau…
-
Hi,
I have used your nice benchmark tool again to compare Kepler K80, Pascal P100 and Volta V100 memory bandwidths.
- It seems that P100 and V100 could increase their Shared Memory + Constant Me…
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**Describe the bug**
After this [commit](https://github.com/facebook/CacheLib/commit/9853dfa0b2e64584fd5765092248abd4a5076e6a) was merged, the script `./contrib/build.sh -d -j -v` no longer works b…
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Hello, thank you for managing the great project!
I found that cachelib provides several traces in [here](https://cachelib.org/docs/Cache_Library_User_Guides/Cachebench_FB_HW_eval#list-of-traces) an…