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* What the feature does
cc #683 but for the disasm part only.
If I understand correctly, one cencern raised in #683 is that the shellcraft module
depends heavily on binutils. But I don't see this c…
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Right now we have colors for these CPU Registers (ver 3.0.9):
![image](https://github.com/horsicq/DIE-engine/assets/765343/8cb5ba37-a2a6-4aa6-ae81-4aa121229c3a)
is it possible to add even more:
…
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### Operating System
Windows 11 Pro 10.0.22631 Build 22631
### x64dbg Version
Sep 10 2024
### Describe the issue
The splitter between the register/disasm view doesn't work and will upon interacti…
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Разве что тот же вопрос, что и к CPU
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I'd absolutely be willing to help with this issue.
One of the main things I target when looking at NDS ROMs is decompiling the code for each processor and using that to understand game logic. Since…
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```
$ ./src/tests/ulpatch_test -f Patch.ftrace_nop -v
Command: ulpatch_test
Exe: /home/sdb/Git/ulpatch/build/src/tests/ulpatch_test
Pid: 22017
PIE: NO
FTO: 8c
MemFD: 4
Disa…
Rtoax updated
3 weeks ago
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Troubleshooting BEQ (branches) offset : +4 ?
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Currently `cargo-show-asm` doesn't detect and can't find merged functions (functions with the same implementation).
I think it is expected to be possible to explore such functions without having to…
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#105541 adds tests that would benefit from having disasm checks to verify coverage of various SVE instruction patterns. However, these tests will be skipped on non-SVE CI machines, meaning no disasm f…
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```
Program received signal SIGSEGV, Segmentation fault.
0x000055555589f221 in falcon_capstone::capstone::Instr::new () at src/capstone.rs:192
192 let detail = unsafe { *instr.detail }…