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### Background and motivation
`GFNI` is supported by Intel in the Ice Lake and newer architectures, and by AMD in Zen 4.
These instructions are known to be useful for cryptography and bit manipula…
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Intel seems to have introduced some new instructions specifically designed for GF(256) operations, including matrix product and the like...
https://networkbuilders.intel.com/solutionslibrary/galois…
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In /Binaries/Tuning.txt the 22-ZN4 ~ Kizuna binary is labeled for Zen5 in the headline and not for Zen4 as in the description:
```
Binary: "22-ZN4 ~ Kizuna" (AMD Zen5)
Required Instructions:
…
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With the addition of the new Ice Lake AVX-512 instruction support in Avo, I've encountered a couple of wrinkles in the naming of the required CPUID features for a given function generated by Avo and t…
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Feature gate: `#![feature(stdarch_x86_avx512)]`
This is a tracking issue for the AVX-512 (and related extensions) intrinsics in `core::arch`.
### Public API
This feature covers all of the int…
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Trying to build ParPar in a docker (alpine:edge, gcc 14) on RISCV64, I get the output with errors below
As it's in *rvv*, I'm assuming it's ParPar specific (not something upstream)?
Is this some…
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We need to present more useful hardware environments about the benchmark runner, like `cat /proc/cpuinfo`, in [Equinix bare metal](https://github.com/open-telemetry/community/blob/main/assets.md#equin…
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Heya,
The library returns invalid keys since `v1.34.1` when running on a machine without AVX instructions.
I've made a small test tool, that just tries [generating some keys from a mnemonic](htt…
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I need to either draw transparent items last or use an order independent transparency system. It doesn't look great right now.
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Hello!
I did some measurements with erasure coding, and I found that EC with a wider stripe usually has a lower encoding throughput. For example, 10+4 has throughput of 6989 MB/s, but 20+4 has thro…