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The BPF ISA defines additional 64bit immediate load instructions. eBPF-for-Windows should add support for type 3 at a minimum. This support can improve the performance of certain BPF programs by elimi…
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https://www.ietf.org/archive/id/draft-ietf-bpf-isa-04.html#name-platform-variables
The BPF ISA at the IETF defines various 64bit immediate loads:
```
5.4. 64-bit immediate instructions
Ins…
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See here:
https://github.com/Vector35/binaryninja-api/blob/7d0b6bc3f49070a10d6257628bbdf93e52d87fed/arch/riscv/src/lib.rs#L1220-L1234
If `rd == rs1`, but is neither `zero` or `ra` (`x0` or `x1` re…
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The BPF ISA defines additional 64bit immediate load instructions. uBPF should add support for type 3 at a minimum.
```
5.4. 64-bit immediate instructions
Instructions with the IMM 'mode' mo…
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I am looking at `assembly` field for instruction and wondering. Should it be in the order/syntax/optionallity of actual assembly language?
Here is an example from here https://github.com/riscv-soft…
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Jumps and branches allow the target address to be a multiple of 2 rather than 4 because compressed instructions can be two bytes. However, in RV{32/64}I, there are no compressed instructions and no wa…
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Currently, the named fields are belong to each instruction and don't carry instruction based semantics.
Here is example of `addi` instruction with `rs1, rd, imm`
```yaml
addi:
long_name: Add…
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`$is` being the basis of jumps is something we should get rid of. I'd like to introduce two new opcodes:
* `JMPA $reg imm` : jump to absolute address in register plus immediate
* `SRAJ $reta reg/imm…
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When the immediate value is too large, the instruction selection drops the immediate into a normal register. This consumes a register name, which is bad because it might mean that some other value get…
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Hallo,
is UTM working with UCS Systeme in IMM mode?
best regards
Stephan