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I'd like to migrate a MPSoC (Ultrascale) project to 4.x, but
https://github.com/FreeRTOS/FreeRTOS-Plus-TCP/blob/main/source/portable/NetworkInterface/xilinx_ultrascale/NetworkInterface.c
is not…
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is there any .xml file available to build a debian system on a Xilinx ultrascale+ mpsoc?
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- **CPU**: Quad Core ARM Cortex-A53 (ARMv8-A)
- **GPU**: Mail 400 MP2
- **Memory**: > 2GB
- **Storage**: QSPI / SDCARD / SATA
- **Features**: Gb Ethernet, USB 2/3, Display Port, HDMI, USB UART
*
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ghost updated
7 years ago
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I there advantage disadvantage of using this adapter vs following this xilinx wiki on cache coherency? https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Cohere…
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Hi @michalvasko we are facing notification send error some times.
we are using following sysrepo and dependent lib versions:
libyang: v2.1.55
netopeer2: v2.1.59
sysrepo: v2.2.60
libnetconf2: v2.1…
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When I try the examples of Vitis-AI master branch in the KR260, the error shown by the following figure bump out.
Actually, I refer to the instruction of https://xilinx.github.io/Vitis-AI/3.0/html/do…
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When I complie the "Hello World " program in the software of the process file generator, it throws me this error
/home/srinisy/ProNoC/mpsoc_work/toolchain/bin/ihex2bin -i image.ihex -o RAM/ram0.bin
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It is my understanding that Antmicro want to support the ZCU10[45] dev boards.
* [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) - Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC
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Hi all, I'm getting Bus error when executing xdputil query.
This is my setup:
- Vitis AI version: Vitis AI 2.0
- Petalinux version: 2021.2
- Board: Ultra96v2
I've installed VART, following h…
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I am trying to incorporate .Net for Xilinx Zynq MPsoc / Petalinux - Are there any resources for somebody like me? Finding a dependency list (the ones used for Ubuntu 22.04 ) would be nice.
Thanks
Rati…