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Hi, I am currently implementing some of the SVE intrinsics in SIMDe (primarily RISCV and emulated version).
However, there are some problems regarding integer divided by zero and floating point NaN/I…
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These are currently broken because the order of elements inside vectors is reversed on big-endian systems: the ARM ABI requires that element 0 is located at the highest address of the vector type. How…
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**Summary**
For, seemingly, all Arm left shift neon intrinsics that accept as a first argument a vector and a constant integer as a second argument, the second argument gets turned into a const vecto…
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This is the ARM NEON version of https://github.com/rust-lang/rust/issues/114479. Example by @beetrees, to be compiled with `--target armv7-unknown-linux-gnueabihf -O -Ctarget-feature=+neon`:
```rust
…
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#### Feature
Add support for the WASM SIMD opcodes in the interpreters.
For my use case I imagine I would use only ARM NEON intrinsics that can run on ARMv7 processors.
I imagine I can create some…
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Feature gate: `#![feature(stdarch_arm_neon_intrinsics)]`
This is a tracking issue for the NEON intrinsics in `core::arch::arm`. This was split off from #90972 which tracked the AArch64 NEON intrins…
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Hi,
As what we know, Cortex-M4F implemented a little set of FPU instructions including VCVT.F32.S32, and GCC did have a builtin intrinsic for it.
But the question is why the intrinsic is only enab…
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Clang/LLVM lowers `a = vget_high_XXX(b)` NEON intrinsics to `EXT Va.16B, Vb.16B, Vb.16B, #8` instead of the `DUP Va.1D, Vb.D[1]` suggested by [ARM NEON intrinsics guide](https://developer.arm.com/arch…
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Feature gate: `#![feature(stdarch_neon_i8mm)]`
This is a tracking issue for NEON intrinsics under the `i8mm` feature.
### Public API
```rust
// core::arch::{arm,aarch64}
fn vs…
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Steps for implementing an intrinsic:
* Select an intrinsic below
* Review `coresimd/arm/neon.rs` and `coresimd/aarch64/neon.rs`
* Consult [ARM official documentation](https://developer.arm.com/te…