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I noticed the `needless_pass_by_value` on the `CPU::new` method, and I wanted to suggest adding a method to `Variant`.
```rust
pub trait Variant {
fn new_cpu(memory: M) -> crate::cpu::CPU
…
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I generated Verilog from the CMOS stick diagram shown below. It is intentionally a useless, nonsense, and broken circuit; I made it to test for infinite loops in the diagramming tool.
I wanted to c…
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1. The gate overlap capacitances seem to be very large. An op analysis for a 5/0.13 NMOS (sg13_lv_nmos) gives cgsol = 3.19575e-15 fF. This corresponds to 0.64 fF/um, about twice as large as in other 0…
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The simulated gm/gds versus gate bias (for various L) for an lv_nmos looks quite odd for short channels (see plot below). Does the measured data support this? I found only plots of gds versus drain bi…
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Support Spice NMOS Models with Levels 1, 2 and 3
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Hello,
I'm running the latest nmos-cpp code. We are observing gradual increase in the memory usage of dbus-daemon.
When we started nmos at that time memory was 2940 bytes(.2 % memory) after 5 h…
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Hello,
I have a question regarding acknowledgment handling in the NMOS-CPP library.
I'm curious if the PATCH action is supposed to wait for acknowledgment from the application to confirm whether…
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Hello,
I have a question.
My goal is to use a reverse proxy and send the reverse proxy IP (for example, 192.168.1.2) to the registry. When accessing this address, the reverse proxy should redire…
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1. I don't understand why you would define epsilon twice:
self.epsilon = techparams['epsilon1']
Cell = self.__class__.__name__
typ = 'N'
hv = False
…
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Instructions like LAX, DCP, AAR, and so on. Commonly used in Commodore 64 demos. Would you consider a pull request adding these?