-
attached testcase reproduces the following problem on latest from `release/19.x` branch
```
. parser at end of file
2. Code generation
3. Running pass 'Function Pass Manager' on …
-
According to the [RISC-V Assembly Programmer's Manual](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc#rvcnorvc), .option norvc is equivalent to .option arch, -c. Howev…
-
https://riscv.org/about/
https://en.wikipedia.org/wiki/RISC-V
**Description:**
RISC-V is a relatively new open standard instruction set architecture (ISA). With only 40 base instructions it is …
-
Clang failes to compile test.S.
test.S is an assembly code that allows the immediate value of the CSR address to be switched at compile time.
test.S
```assembly
#define CSR_STVEC 0x105
#define …
-
The prior RISC-V ISA Specification (20191213) had a chapter 25, "RISC-V Assembly Programmer’s Handbook" which had a table listing many/most pseudoinstructions. This is no longer present in the most re…
-
Fantastic work! I run into this webpage when searching for SMMLA assembly in Google. Your categorization is far more clear and easy-to-use than Arm's data sheet.
As a programmer, I noticed that rec…
-
### Is your feature request related to a problem? Please describe
I would like to compile rvv program online and check the assembly code, by risc-v GCC or clang.
### Describe the solution you'd …
-
When reviewing https://github.com/seL4/seL4/pull/344, I was wondering if the fastpath code In traps.S could be optimized a bit further. There is
```
#ifdef CONFIG_FASTPATH
li t3, SYSCALL_REPLY_R…
-
Hi Tommy,
Thanks for sharing a very good Repo. I am interested to understand how you generated the binaries
[https://github.com/TommyWu-fdgkhdkgh/spike-vp/tree/main/sw](url)
Can you please pro…
-
I'm not sure if you have access to RVV hardware, so I thought I'd offer my help in that regard:
C908 encode:
```
input size: 12582912, output size: 16777216
number of iterations: 10
We report t…