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**What are you trying to do?**
With the SiFive HiFive Premier P550 there is a first RISC-V board available that supports KVM.
We should support running VMs with multipass on it.
**What's your p…
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## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/12061757831
## Patch information
Applied patches: 1 -> 1
A…
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## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/12061757831
## Patch information
Applied patches: 1 -> 2
A…
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qemu 9.2 has sifive's patches for significantly faster V that should let us start using more V.
we should also start enabling other extensions.
Zfa would let enh@ simplify some assembler.
Zicfilp a…
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Input:
```mlir
scf.if %true {
%true = arith.constant true
}
```
This crashes on release builds, ASAN reports heap-use-after-free. Found via fuzzing.
ASAN report
```
=================…
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**[SiFive](https://www.sifive.com/)**
SiFive, Inc. is a fabless semiconductor company and provider of commercial RISC-V processor IP and silicon chips based on the RISC-V instruction set ar…
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I used the test drive which posted in this repo: "https://github.com/vexingcodes/spike-plugin" to test the output
With this command line:
"spike -m1 --extlib=/tmp/riscvtoolchain/lib/libspikedevic…
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Please add support for BL602/BL604 made by BouffaloLab
> The BL602 is a general purpose microcontroller based on the “SiFive E24 Core” RISC-V processor.
Notice that it's only _based on_ the SiFi…
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Hello,
we are a group who is interested in adding another target for solokeys, namely RISC-V boards by SiFive. We are at the start of the project, however we'd wish to eventually upstream the chang…
ljrk0 updated
4 years ago
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As the upstream software RISC-V support has come a long way, there is the real possibility of a dockerized approach to Ethereum staking on RISC-V boards like Sifive, Milk-V, LicheePI.