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Is there any documentation or sample code?
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Your publication neoSYCL: a SYCL implementation for SX-Aurora TSUBASA reads
> neoSYCL needs to separate the host and kernel codes so that they can be compiled with different
compilers. In the case…
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### Compiler name
LLVM Clang
### Compiler version
14.0.0, target VE
### Compiler language
C++
### Compiler homepage
https://github.com/llvm/llvm-project/blob/llvmorg-14.0.0/llvm/CMakeLists.txt#…
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Some modern instructions set architectures (ISAs) such as X86-64, Power9, MIPS and SPARCv9 support SIMD instructions. Others like ARMv8 and RISC-V support far more complete vector extensions (VE) whil…
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It would be a great addition to integrate Spores3 into the actor library, such that the "behaviors" are "spores".
An issue was encountered on a small test, as there seemed to be some issues to inte…
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### Vector
A vector-based list is a list that store elements in continuous area.
Vector can improve cache performane and have smaller constant factor.
Whether it's faster than list depends on the…
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The NEC Aurora Tsubasa SX exports a set of sensors to the outside world via sysfs.
The base path for all sensors is `/sys/class/ve/ve[X]/sensor_[Y]`, where X is the ID of the Accelerator card and Y…
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compiling the following code with llc:
```llvm
; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "adler.707c2e002c6e23cc-cgu.0"
target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:6…
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See its [homepage](https://sx-aurora.github.io/) and LLVM support is [upstream](https://github.com/llvm/llvm-project/tree/main/llvm/lib/Target/VE). The architecture documentation is at https://sxauror…
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I have started to use an unfamiliar NEC vector-type supercomputer (SX-Aurora TSUBASA) and have very little knowledge of compiling on it.
I am wondering if anyone has successfully compiled JDFTx on …