-
- [x] I have reviewed this project's [contribution guidelines](https://github.com/SystemRDL/systemrdl-compiler/blob/main/CONTRIBUTING.md)
**Describe the bug**
In the following code:
```
`ifd…
-
Can you add support for the register description language SystemRDL?
Here is a link to the standard https://www.accellera.org/downloads/standards/systemrdl.
There is also a great open-source commu…
-
Hello,
Regarding the 'external' type, I don't find the specification 2.0 to be super clear for fields (and signals).
For example, it is stated in 9.6.1:
> A field with an onread value of ruse…
-
I've been trying to run the https://github.com/SystemRDL/RALBot-html/blob/master/example/turboencabulator.rdl example to see if I can get Ordt to parse the same file.
As it appears, Ordt fails to p…
-
Hi,
I was looking for something like `regbits` since yesterday :).
Not really for a long time, so I am not sure yet if I found what I was looking for.
Additionally C++ is not a language I write c…
jeras updated
3 years ago
-
Currently the importer API only allows building components with "regular" property values.
Add support for assigning instance and property references to component properties.
Some considerations t…
-
**Describe the bug**
Dear systemrdl-compiler community,
I'm encountering what I believe is a bug. The RDLImporter class as a method called add_child() but it does not support adding signals to a…
-
Im using systemrdl to implement my cores CSRs, with a generator that consumes a rdl file and compiles it to systemverilog files and thats working fine.
Now lets say I have 3 cores: A, B and C. The …
-
### Description
Dear Maintainers,
I am writing to request the addition of support for generating IEEE/Accellera IPXACT XML Schema in `regtool`.
**Background:**
IPXACT is an XML-based standar…
-
```
regfile modules_l_reset_0 {
default regwidth = 8;
reg {
field {} PORT7[7:7] = 0;
field {} PORT6[6:6] = 0;
field {} PORT5[5:5] = 0;
field {} PORT4[4:4…