A4091 / a4091-logic

GAL source code for A4091 project
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Enable Early Byte-Lane Option #1

Closed reinauer closed 1 year ago

reinauer commented 1 year ago

This enables the Zorro III Early Byte-Lane option, which results in an overall speed increase of about 10% on the A4091.

From the Zorro III Bus Timing Addendum

2.4 Early Byte-Lane Option

There is now an optional early byte lane mode for full cycles. A bus master can, optionally, drive /DS3-/DS0 according to normal address time signal timing. Slaves that don't support this mode see /DSN at the normal data-time, qualified by DOE. Slaves that do support this mode can latch /DSN on the falling edge of /FCS. If at least one strobe is valid, the slave gets a valid early byte-lane enable, and may use /DSn during data time for write data latching. If none are valid, it will be necessary to use /DSn at data time for sizing information.

Found by dorken @ a1k