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ADSD-SoC-FPGA / Code

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Make PLL naming consistent with textbook instructions #6

Closed LRitzdorf closed 9 months ago

LRitzdorf commented 9 months ago

This PR updates the main constraints file so that it uses the correct component path to reach the "sys_clk from MCLK" PLL. This is part of the AD1939 subsystem, not the top-level QSYS system as is currently listed.

LRitzdorf commented 9 months ago

The constraints file could probably use a larger cleanup effort at some point (since it contains a lot of commented-out code, and not much relevant explanation), but that's not directly relevant to this issue.

tvannoy commented 9 months ago

The constraints file could probably use a larger cleanup effort at some point (since it contains a lot of commented-out code, and not much relevant explanation), but that's not directly relevant to this issue.

The current timing constraints file is certainly incomplete. In my memory, it has never passed timing verification since it was first created. The person who created the original constraints did the best they could with the knowledge and time available, starting from the DE10 Nano constraints provided by Terasic.

Neither Ross nor I have much expertise in timing constraints. Teaching timing constraints is a long-term goal, but we rarely have time to delve into it.

There have been a few rare occasions where the incorrect timing constraints masked an actual timing failure, but that has generally been easy enough to discover.

If you want to become a timing constraints wizard and fix the constraints, be my guest.