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Assertion `round(HPWL_extend) == round(HPWL_ILP)' failed #1266

Closed rajivbishwokarma closed 1 year ago

rajivbishwokarma commented 1 year ago

Complete error generated:

python3: /home/rb/work/ALIGN-public/PlaceRouteHierFlow/placer/ILP_solver.cpp:3110: double ILP_solver::GenerateValidSolution(const design&, const SeqPair&, const PnRDB::Drc_info&, int): Assertion `round(HPWL_extend) == round(HPWL_ILP)' failed.

Recreating the error

  1. Use the following netlist to run schematic2layout.py.
.subckt fn_sim A B C D E F Y vdd GND
M1 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=3
M2 net3 B vdd vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=3
M3 net2 C net1 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=3
M4 net2 D net3 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=3
M5 Y E net2 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=3
M6 Y F net2 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=3
M7 Y A net4 GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=3
M8 Y C net4 GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=3
M9 Y E net5 GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=3
M10 net4 B GND GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=3
M11 net4 D GND GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=3
M12 net5 F GND GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=3
.ends

  1. Run schematic2layout.py ../fn_sim -p ../pdks/ALIGN-pdk-sky130/SKY130_PDK

  2. Run time log

align.main INFO : Reading netlist: /home/rb/work/ALIGN-public/fn_sim/fn_sim.sp subckt=FN_SIM, flat=0
align.compiler.compiler INFO : Starting topology identification...
align.compiler.compiler INFO : Power and ground nets not found. Power grid will not be constructed.
align.compiler.compiler INFO : Completed topology identification.
align.pnr.main INFO : Running Place & Route for FN_SIM
align.pnr.build_pnr_model INFO : Reading contraint json file FN_SIM.pnr.const.json
align.pnr.build_pnr_model INFO : Reading contraint json file FN_SIM.pnr.const.json
align.pnr.placer INFO : Starting bottom-up placement on FN_SIM 0
PnR.placer.Placer.PlacementCoreAspectRatio_ILP INFO : Required 1 perturbations to generate a feasible solution.
python3: /home/rb/work/ALIGN-public/PlaceRouteHierFlow/placer/ILP_solver.cpp:3110: double ILP_solver::GenerateValidSolution(const design&, const SeqPair&, const PnRDB::Drc_info&, int): Assertion `round(HPWL_extend) == round(HPWL_ILP)' failed.
Aborted (core dumped)

  1. Output log image image

  2. Running schematic2layout.py with m=8 in the input netlist gets stuck in the following step.

PnR.placer.Placer.PlacementCoreAspectRatio_ILP INFO : Required 1 perturbations to generate a feasible solution.

Modified netlist:

.subckt fn_sim A B C D E F Y vdd GND
M1 net1 A vdd vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=8
M2 net3 B vdd vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=8
M3 net2 C net1 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=8
M4 net2 D net3 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=8
M5 Y E net2 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=8
M6 Y F net2 vdd sky130_fd_pr__pfet_01v8 L=150e-9 W=21e-7 nf=10 m=8
M7 Y A net4 GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=8
M8 Y C net4 GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=8
M9 Y E net5 GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=8
M10 net4 B GND GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=8
M11 net4 D GND GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=8
M12 net5 F GND GND sky130_fd_pr__nfet_01v8 L=150e-9 W=10.5e-7 nf=10 m=8
.ends
  1. Stuck at the following step: image
rajivbishwokarma commented 1 year ago

I am not sure what I am doing wrong here? Is there something wrong with the input spice netlist?

kkunal1408 commented 1 year ago

The netlist looks fine. There is an issue with the auto-constraint generation. I will debug that, in the meantime, you can proceed by turning off auto constraints by adding a file "fn_sim.const.json" with the content:

[
        {"constraint": "PowerPorts", "ports": ["VDD"]},
        {"constraint": "GroundPorts", "ports": ["GND"]},  
        {"constraint": "ConfigureCompiler", "auto_constraint": false}
]

You can also add more manual constraints using the options listed here: https://align-analoglayout.github.io/ALIGN-public/notes/const.html#

kkunal1408 commented 1 year ago

Can you provide a rough schematic or layout plan so that I can debug the auto-generated constraints?

rajivbishwokarma commented 1 year ago

I solved this issue by connecting the bulk terminals of the transistors to their sources. In the previous schematic, I was connecting the bulk terminals to the VDD for PMOS and to GND for NMOS.

The following schematic with the bulk terminals of PMOS (C, D, E, F) connected to VDD and the bulk terminal of NMOS (A, C, E) connected to GND was causing the above issue. This circuit fixed it.

image
kkunal1408 commented 1 year ago

Thanks a lot. I will check for the error with the previous circuit.

syedimaduddin commented 1 year ago

I am also facing the same error as @rajivbishwokarma faced with the below schematic of 1bit ADC adc_prelayout_schematic

I extracted the netlist from above schematic and converted it to the required format for ALIGN as below

.subckt adc_1bit VSS VDD OUT INN INP
XM1 net2 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM2 OUT net2 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM3 net1 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM4 net3 net3 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM5 net1 INN net4 net4 sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM6 net2 INP net4 net4 sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM7 net4 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM8 OUT net3 VSS VSS sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=2
XM9 net3 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=150e-09 w=10.5e-7 nf=2
.ends adc_1bit

And facing the below error while running ALIGN for sky130 pdk Error

kkunal1408 commented 1 year ago

The netlist looks fine. There is an issue with the auto-constraint generation. I will debug that, in the meantime, you can proceed by turning off auto constraints by adding a file "fn_sim.const.json" with the content:

[
        {"constraint": "PowerPorts", "ports": ["VDD"]},
        {"constraint": "GroundPorts", "ports": ["GND"]},  
        {"constraint": "ConfigureCompiler", "auto_constraint": false}
]

You can also add more manual constraints using the options listed here: https://align-analoglayout.github.io/ALIGN-public/notes/const.html#

@syedimaduddin Does this solution work for you?

syedimaduddin commented 1 year ago

@kkunal1408 the layout is created using your mentioned method, but the post-layout simulation is different from the pre-layout simulation.

As there are still some errors skipped in the layout, I think it was not created successfully

kkunal1408 commented 1 year ago

Are you talking about performance degradation or any specific failures?

syedimaduddin commented 1 year ago

Actually @kkunal1408, my pre-layout netlist of 1-bit ADC is

** sch_path: /home/syedimaduddin/Desktop/VSD_PD_Research_Program/Week-5/xschem/adc_1bit.sch
**.subckt adc_1bit VSS VDD OUT INN INP
*.iopin VSS
*.iopin VDD
*.opin OUT
*.ipin INN
*.ipin INP
XM1 net2 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM2 OUT net2 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM3 net1 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM4 net3 net3 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM5 net1 INN net4 net4 sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM6 net2 INP net4 net4 sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM7 net4 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM8 OUT net3 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM9 net3 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
V1 VDD GND 1.8
.save i(v1)
V2 VSS GND 0
.save i(v2)
V3 INP GND sin(0.9 0.9 100Meg)
.save i(v3)
V4 INN GND 0.9
.save i(v4)
**** begin user architecture code
.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
.control
save all
tran 0.01n 100n
plot inp out inn
.endc
**** end user architecture code
**.ends
.GLOBAL GND
.end

And my pre-layout simulation using ngspice is Pre-layout

By converting .spice file to .sp file for ALIGN, my netlist becomes

.subckt adc_1bit VSS VDD OUT INN INP
XM1 net2 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM2 OUT net2 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM3 net1 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM4 net3 net3 VDD VDD sky130_fd_pr__pfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM5 net1 INN net4 net4 sky130_fd_pr__nfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM6 net2 INP net4 net4 sky130_fd_pr__nfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM7 net4 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM8 OUT net3 VSS VSS sky130_fd_pr__nfet_01v8 L=150e-9 W=8.4e-7 nf=4
XM9 net3 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=150e-9 W=8.4e-7 nf=4
.ends adc_1bit

And my adc_1bit.const.json file is 

[
        {"constraint": "PowerPorts", "ports": ["VDD"]},
        {"constraint": "GroundPorts", "ports": ["VSS"]},  
        {"constraint": "ConfigureCompiler", "auto_constraint": false}
]

And then I have extracted the netlist from gds file of layout generated by ALIGN using following commands in Magic tool

extract do local
extract all
ext2spice hierarchy off
ext2spice scale off
ext2spice cthresh 0 rthresh 0
ext2spice

My post layout netlist comes out is

* SPICE3 file created from ADC_1BIT_0.ext - technology: sky130A

X1 VSS VDD OUT INN INP adc_1bit

V1 VDD GND 1.8
.save i(v1)
V2 VSS GND 0
.save i(v2)
V3 INP GND sin(0.9 0.9 100Meg)
.save i(v3)
V4 INN GND 0.9
.save i(v4)
**** begin user architecture code
.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
.control
save all
tran 0.01n 100n
plot inp out inn
.endc
**** end user architecture code

.subckt adc_1bit VSS VDD OUT INN INP
X0 m1_1602_1484# m1_1602_1484# VDD VDD sky130_fd_pr__pfet_01v8 ad=4.704e+11p pd=4.48e+06u as=2.5116e+12p ps=2.446e+07u w=840000u l=150000u
X1 VDD m1_1602_1484# m1_1602_1484# VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X2 m1_1602_1484# m1_1602_1484# VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X3 VDD m1_1602_1484# m1_1602_1484# VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X4 VSS NMOS_S_74334133_X2_Y1_1679372695_0/a_200_252# m1_602_1316# VSS sky130_fd_pr__nfet_01v8 ad=3.6624e+12p pd=3.56e+07u as=4.704e+11p ps=4.48e+06u w=840000u l=150000u
X5 m1_602_1316# NMOS_S_74334133_X2_Y1_1679372695_0/a_200_252# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X6 VSS NMOS_S_74334133_X2_Y1_1679372695_0/a_200_252# m1_602_1316# VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X7 m1_602_1316# NMOS_S_74334133_X2_Y1_1679372695_0/a_200_252# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X8 VSS NMOS_S_74334133_X2_Y1_1679372695_1/a_200_252# m1_312_1484# VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.704e+11p ps=4.48e+06u w=840000u l=150000u
X9 m1_312_1484# NMOS_S_74334133_X2_Y1_1679372695_1/a_200_252# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X10 VSS NMOS_S_74334133_X2_Y1_1679372695_1/a_200_252# m1_312_1484# VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X11 m1_312_1484# NMOS_S_74334133_X2_Y1_1679372695_1/a_200_252# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X12 VSS m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X13 VSS m1_1602_1484# m1_1602_1484# VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.704e+11p ps=4.48e+06u w=840000u l=150000u
X14 VSS m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X15 m1_1602_1484# m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X16 VSS m1_1602_1484# m1_1602_1484# VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X17 VSS m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X18 VSS m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X19 m1_1602_1484# m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X20 VSS m1_1602_1484# OUT VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=4.704e+11p ps=4.48e+06u w=840000u l=150000u
X21 OUT m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X22 VSS m1_1602_1484# OUT VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X23 OUT m1_1602_1484# VSS VSS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X24 OUT m1_602_1316# VDD VDD sky130_fd_pr__pfet_01v8 ad=4.704e+11p pd=4.48e+06u as=0p ps=0u w=840000u l=150000u
X25 VDD m1_602_1316# OUT VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X26 OUT m1_602_1316# VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X27 VDD m1_602_1316# OUT VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X28 VDD m1_312_1484# m1_312_1484# VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=4.704e+11p ps=4.48e+06u w=840000u l=150000u
X29 m1_602_1316# m1_312_1484# VDD VDD sky130_fd_pr__pfet_01v8 ad=4.704e+11p pd=4.48e+06u as=0p ps=0u w=840000u l=150000u
X30 m1_312_1484# m1_312_1484# VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X31 VDD m1_312_1484# m1_312_1484# VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X32 VDD m1_312_1484# m1_602_1316# VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X33 m1_602_1316# m1_312_1484# VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X34 m1_312_1484# m1_312_1484# VDD VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
X35 VDD m1_312_1484# m1_602_1316# VDD sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=840000u l=150000u
C0 m1_1602_1484# INP 0.05fF
C1 VDD INN 0.01fF
C2 OUT INP 0.00fF
C3 m1_312_1484# VDD 4.49fF
C4 m1_602_1316# NMOS_S_74334133_X2_Y1_1679372695_0/a_200_252# 0.22fF
C5 VDD VSS 3.14fF
C6 m1_1602_1484# VDD 4.26fF
C7 m1_602_1316# INN 0.00fF
C8 OUT VDD 1.75fF
C9 m1_602_1316# m1_312_1484# 0.68fF
C10 m1_602_1316# VSS 0.83fF
C11 VDD INP 0.04fF
C12 m1_602_1316# m1_1602_1484# 0.60fF
C13 m1_602_1316# OUT 0.23fF
C14 m1_312_1484# INN 0.01fF
C15 m1_602_1316# INP 0.05fF
C16 INN VSS 0.03fF
C17 m1_312_1484# VSS 0.23fF
C18 m1_1602_1484# INN 0.00fF
C19 m1_1602_1484# m1_312_1484# 0.05fF
C20 m1_312_1484# NMOS_S_74334133_X2_Y1_1679372695_1/a_200_252# 0.22fF
C21 m1_1602_1484# VSS 1.27fF
C22 m1_312_1484# OUT 0.00fF
C23 m1_602_1316# VDD 4.77fF
C24 INP INN 0.04fF
C25 OUT VSS 0.29fF
C26 m1_1602_1484# OUT 0.24fF
C27 INP VSS 0.07fF
C28 VSS 0 0.85fF
C29 OUT 0 1.21fF
C30 VDD 0 12.40fF
C31 m1_1602_1484# 0 4.67fF
C32 m1_312_1484# 0 1.06fF
C33 NMOS_S_74334133_X2_Y1_1679372695_1/a_200_252# 0 1.47fF
C34 NMOS_S_74334133_X2_Y1_1679372695_0/a_200_252# 0 1.47fF
.ends

And my post-layout simulation is Post-layout

You can see that my pre-layout simulation is not the same as my post-layout simulation for 1-bit ADC. So, I'm saying that it could be caused by error skipping with the constraint you mentioned.

kkunal1408 commented 1 year ago

@syedimaduddin For the schematic simulation, can you try using the updated parameters which you used as input for ALIGN. e.g. this is one of your original device parameter XM9 net3 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 Requirement for ALIGN is that for a device nf should be even. This is your modified parameter which you are feeding as input to ALIGN XM9 net3 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=150e-9 W=8.4e-7 nf=4 When you increased your nf to 4 you are changing your circuit device parameters (L modification is only unit change but not sure why you modified your W). While doing your input SPICE simulations you need to incorporate these changes. Can you please confirm your simulation results after these modifications.

syedimaduddin commented 1 year ago

@kkunal1408 I was trying by putting different values of W and nf. For the same W and nf values in pre-layout simulation and post-layout simulation, I got the below results.

Pre-layout netlist adc_pre_layout

Pre-layout simulation pre_layout_adc

Netlist to ALIGN adc_sp_file

Post-layout netlist adc_post_layout

Post-layout simulation post_layout_adc

The results are the same as before.

syedimaduddin commented 1 year ago

@kkunal1408 My problem has been solved after I removed ALIGN from my PC and reinstalled it. An incomplete installation could have caused the error. Maybe I missed some steps when installing ALIGN last time.

This time, I have followed below repositories completely: https://github.com/ALIGN-analoglayout/ALIGN-public https://github.com/ALIGN-analoglayout/ALIGN-pdk-sky130

kkunal1408 commented 1 year ago

Thanks for letting us know.