About bulk pdks, I dont have the fin layer in my pdk.

[Nakiana]

Hello. Regarding bulk PDKs, my PDK does not include the fin layer. Additionally, I do not utilize the process parameters in the .sp file nfin=8 nf=4. How should I proceed with using ALIGN?

Furthermore, I noticed the sentence "We will remove the 'Fin' layer for bulk PDKs in future releases" in the PDK Abstraction Guide.pdf. Does this mean ALIGN layout generator can only be used with finFET processes for now?

[srini229]

ALIGN supports bulk PDKs with the Fin layer used as a place holder for certain assumptions in the MOS layout generator. Example mock pdks in the pdks directory: Bulk65nm_Mock_PDK and Bulk45nm_Mock_PDK

[Nakiana]

ALIGN supports bulk PDKs with the Fin layer used as a place holder for certain assumptions in the MOS layout generator. Example mock pdks in the pdks directory: Bulk65nm_Mock_PDK and Bulk45nm_Mock_PDK

Could you please clarify ALIGN how to distinguish between the Finlayer when used as a placeholder and when it functions as a useful layer in FinFET technology? Additionally, if I'm utilizing the Bulk45nm_Mock_PDK, what should the parameters nfin=8 nf=4 be set to? Are there any specific rules for setting these parameters?

[Nakiana]

@srini229 Could you please clarify ALIGN how to distinguish between the Finlayer when used as a placeholder and when it functions as a useful layer in FinFET technology? Additionally, if I'm utilizing the Bulk45nm_Mock_PDK, what should the parameters nfin=8 nf=4 be set to? Are there any specific rules for setting these parameters?

[kkunal1408]

The update marked in the slides has already been included in the latest code version. For Bulk45nm_Mock_PDK , ALIGN just uses W, NF (number of fingers), and M (multiplier) parameters. Here is an example of a SPICE netlist in Bulk technology five_transistor_ota_Bulk.sp

You can look at this code to understand the handling of these parameters (gen_param.py).

[Nakiana]

@kkunal1408 Oh, I think I understand now. Thank you very much!