error when running my own circuit netlist

[AmrMohamedRashed]

I am trying to run my own circuit netlist, generated from cadence virtuous, but the tool fails to run it successfully. The error message is as follow:

/home/cadence/my_project/MASTER/ALIGN-public/align/gui/mockup.py:5: UserWarning: The dash_html_components package is deprecated. Please replace import dash_html_components as html with from dash import html import dash_html_components as html /home/cadence/my_project/MASTER/ALIGN-public/align/gui/mockup.py:6: UserWarning: The dash_core_components package is deprecated. Please replace import dash_core_components as dcc with from dash import dcc import dash_core_components as dcc align.main INFO : Running flow steps ['1_topology', '2_primitives', '3_pnr:prep', '3_pnr:place', '3_pnr:route', '3_pnr:check'] align.cmdline ERROR : Fatal Error. Cannot proceed Traceback (most recent call last): File "/home/cadence/my_project/MASTER/ALIGN-public/align/cmdline.py", line 146, in parse_args return schematic2layout(**vars(arguments)) File "/home/cadence/my_project/MASTER/ALIGN-public/align/main.py", line 285, in schematic2layout netlist = extract_netlist_files(netlist_dir,netlist_file) File "/home/cadence/my_project/MASTER/ALIGN-public/align/main.py", line 221, in extract_netlist_files assert len(netlist_files) == 1, "Only one .sp file allowed" AssertionError: Only one .sp file allowed

here is the circuit netlist:

.subckt DoubleTailSenseAmplifier CLK CLK_B DIN DIP VDD VIN VIP VON VOP VSS *.PININFO CLK:I CLK_B:I VIN:I VIP:I DIN:O DIP:O VON:O VOP:O VDD:B VSS:B .param no_of_fin = 10 TAIL_P_1 REGEN_SOURCE CLK_B VDD VDD pmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 TAIL_P_2 REGEN_SOURCE CLK_B VDD VDD pmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 INV_P_P VOP VON REGEN_SOURCE VDD pmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 INV_P_N VON VOP REGEN_SOURCE VDD pmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 LOAD_P DIN CLK VDD VDD pmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 LOAD_N DIP CLK VDD VDD pmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 RESET_P VOP DIN VSS VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 RESET_N VON DIP VSS VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 INV_N_P VOP VON VSS VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 INV_N_N VON VOP VSS VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 IN_P DIN VIP PRE_AMP_SOURCE VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 IN_N DIP VIN PRE_AMP_SOURCE VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 TAIL_2 PRE_AMP_SOURCE CLK VSS VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 TAIL_1 PRE_AMP_SOURCE CLK VSS VSS nmos_rvt w=270e-9 l=20e-9 nfin=2 nf=2 .ends DoubleTailSenseAmplifier

may I know where is the error?

[kkunal1408]

The error is due to the directory structure. For simplicity, our requirement is that the directory_name = SPICE_file_name = Design_name. In the directory, there should be only one file with ".sp" suffix.

In the netlist we have another requirement that all transistor names should start with "m/M" e.g. TAIL_P_1 --> MTAIL_P_1 othewise you will see another error: "NotImplementedError: ('TAIL_P_1', ['REGEN_SOURCE', 'CLK_B', 'VDD', 'VDD', 'PMOS_RVT'], {'L': 2e-08, 'NFIN': 2, 'W': 2.7e-07, 'NF': 2}, 'is not yet recognized by parser')"

[AmrMohamedRashed]

@kkunal1408 : thank you for your help really appreciated. I have one more note: VSS or GND should be replaced with 0.

[kkunal1408]

Thats not a requirement. If you want to define it as a gnd net you need to define that in a setup file. For reference look into this setup file.