ARM-software / CMSIS-RTX

RTX5 real time kernel for Arm Cortex-based embedded systems (spin-off from CMSIS_5)
https://arm-software.github.io/CMSIS-RTX/
Apache License 2.0
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Clarify the context size of threads that never use FP on Cortex-M4F. #47

Open apricot-azumi opened 2 months ago

apricot-azumi commented 2 months ago

For Cortex-M4/M7 with FP the thread context requires 200 bytes on the local stack. For these devices the default stack space should be increased to a minimum of 300 bytes.

In my application only a single thread uses floats. Is it safe to use smaller stack size for all other threads?

I believe EXC_RETURN is checked before pushing S16-S31. Is this relevent?

apricot-azumi commented 2 months ago

I believe we can theoretically omit saving S16-S31 if only one thread uses floats, according to https://developer.arm.com/documentation/dai0298/a/ Section 4.2

Besides the question I asked, is it feasible to add a compile flag and implement this?

RobertRostohar commented 2 months ago

Floating point registers are pushed to stack only for threads which used floating point instructions. Registers S0-S15 and FPSCR are pushed by hardware on exception entry and registers S16-S31 by RTX on thread switch.

Therefore smaller stack can be used for threads which do not use floating point instructions.

If a single thread is using floating point instructions and interrupt handlers don't use floating point instructions, then floating point registers don't need to be saved at all. This can be achieved by setting FPCCR bits ASPEN and LSPEN to 0 (from user code) as explained in section 4.2 of the mentioned document. In that case hardware will not save floating point registers (when the thread which used floating point instructions is interrupted) and RTX will also not save the remaining floating point registers on thread switch. This is already implemented and no additional compile flags should be needed.