I just noticed the new MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE etc defines.
A few issues with these, in descending order of importance:
The TR transient indication is inverted. Bit 3 needs to be set for transient.
The 0b binary prefix requires a very recent language standard or a compiler extension.
Shouldn't they have an ARM_ prefix to match surrounding defines?
But is the OUTER_ and INNER_ necessary?
And as an aside, just for anyone happening to search and end up here - it's not specified anywhere what the "transient" flags of the default memory map are. Apparently the default regions are transient in the M55, which surprised me.
Would you mind raising a PR with your proposed changes?
Perhaps switch over to ARM-software/CMSIS6 and we leave it unchanged here. Adding `ARM` prefix might be a good idea but would break backward compatibility.
I just noticed the new
MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE
etc defines.A few issues with these, in descending order of importance:
TR
transient indication is inverted. Bit 3 needs to be set for transient.0b
binary prefix requires a very recent language standard or a compiler extension.ARM_
prefix to match surrounding defines?OUTER_
andINNER_
necessary?And as an aside, just for anyone happening to search and end up here - it's not specified anywhere what the "transient" flags of the default memory map are. Apparently the default regions are transient in the M55, which surprised me.