Misra violation in mpu_armv7.h, mpu_armv8.h

[CanastraRF]

When I check mpu_armv7.h, mpu_armv8.h against Misra rules C++ 2008 I get some Violation in the following lines: #define ARM_MPU_AP_NONE 0u #define ARM_MPU_AP_PRIV 1u #define ARM_MPU_AP_URO 2u #define ARM_MPU_AP_FULL 3u #define ARM_MPU_AP_PRO 5u #define ARM_MPU_AP_RO 6u ... MPU->RASR = 0u; ... for (i = 0u; i < len; ++i) ...

Rule 2-13-4 Literal suffixies shall be upper case

and also in the following files:

\Core\Include\cmsis_compiler.h \DSP\DSP_Lib_TestSuite\Common\src\transform_tests\cfft_family_tests.c \DSP\DSP_Lib_TestSuite\Common\src\transform_tests\rfft_fast_tests.c \DSP\DSP_Lib_TestSuite\Common\src\transform_tests\rfft_tests.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\biquad.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\correlate.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\fir.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\fir_decimate.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\fir_interpolate.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\fir_lattice.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\fir_sparse.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\iir_lattice.c \DSP\DSP_Lib_TestSuite\RefLibs\src\FilteringFunctions\lms.c \DSP\Include\arm_math.h \DSP\Source\BasicMathFunctions\arm_abs_f32.c \DSP\Source\BasicMathFunctions\arm_abs_q15.c \DSP\Source\BasicMathFunctions\arm_abs_q31.c \DSP\Source\BasicMathFunctions\arm_abs_q7.c \DSP\Source\BasicMathFunctions\arm_add_f32.c \DSP\Source\BasicMathFunctions\arm_add_q15.c \DSP\Source\BasicMathFunctions\arm_add_q31.c \DSP\Source\BasicMathFunctions\arm_add_q7.c \DSP\Source\BasicMathFunctions\arm_dot_prod_f32.c \DSP\Source\BasicMathFunctions\arm_dot_prod_q15.c \DSP\Source\BasicMathFunctions\arm_dot_prod_q31.c \DSP\Source\BasicMathFunctions\arm_dot_prod_q7.c \DSP\Source\BasicMathFunctions\arm_mult_f32.c \DSP\Source\BasicMathFunctions\arm_mult_q15.c \DSP\Source\BasicMathFunctions\arm_mult_q31.c \DSP\Source\BasicMathFunctions\arm_mult_q7.c \DSP\Source\BasicMathFunctions\arm_negate_f32.c \DSP\Source\BasicMathFunctions\arm_negate_q15.c \DSP\Source\BasicMathFunctions\arm_negate_q31.c \DSP\Source\BasicMathFunctions\arm_negate_q7.c \DSP\Source\BasicMathFunctions\arm_offset_f32.c \DSP\Source\BasicMathFunctions\arm_offset_q15.c \DSP\Source\BasicMathFunctions\arm_offset_q31.c \DSP\Source\BasicMathFunctions\arm_offset_q7.c \DSP\Source\BasicMathFunctions\arm_scale_f32.c \DSP\Source\BasicMathFunctions\arm_scale_q15.c \DSP\Source\BasicMathFunctions\arm_scale_q31.c \DSP\Source\BasicMathFunctions\arm_scale_q7.c \DSP\Source\BasicMathFunctions\arm_shift_q15.c \DSP\Source\BasicMathFunctions\arm_shift_q31.c \DSP\Source\BasicMathFunctions\arm_shift_q7.c \DSP\Source\BasicMathFunctions\arm_sub_f32.c \DSP\Source\BasicMathFunctions\arm_sub_q15.c \DSP\Source\BasicMathFunctions\arm_sub_q31.c \DSP\Source\BasicMathFunctions\arm_sub_q7.c \DSP\Source\ComplexMathFunctions\arm_cmplx_conj_f32.c \DSP\Source\ComplexMathFunctions\arm_cmplx_conj_q15.c \DSP\Source\ComplexMathFunctions\arm_cmplx_conj_q31.c \DSP\Source\ComplexMathFunctions\arm_cmplx_dot_prod_f32.c \DSP\Source\ComplexMathFunctions\arm_cmplx_dot_prod_q15.c \DSP\Source\ComplexMathFunctions\arm_cmplx_dot_prod_q31.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mag_f32.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mag_q15.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mag_q31.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mag_squared_f32.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mag_squared_q15.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mag_squared_q31.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_f32.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_q15.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mult_cmplx_q31.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mult_real_f32.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mult_real_q15.c \DSP\Source\ComplexMathFunctions\arm_cmplx_mult_real_q31.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df1_32x64_q31.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df1_f32.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df1_fast_q15.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df1_fast_q31.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df1_q15.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df1_q31.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df2T_f32.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_df2T_f64.c \DSP\Source\FilteringFunctions\arm_biquad_cascade_stereo_df2T_f32.c \DSP\Source\FilteringFunctions\arm_conv_f32.c \DSP\Source\FilteringFunctions\arm_conv_fast_opt_q15.c \DSP\Source\FilteringFunctions\arm_conv_fast_q15.c \DSP\Source\FilteringFunctions\arm_conv_fast_q31.c \DSP\Source\FilteringFunctions\arm_conv_opt_q15.c \DSP\Source\FilteringFunctions\arm_conv_opt_q7.c \DSP\Source\FilteringFunctions\arm_conv_partial_f32.c \DSP\Source\FilteringFunctions\arm_conv_partial_fast_opt_q15.c \DSP\Source\FilteringFunctions\arm_conv_partial_fast_q15.c \DSP\Source\FilteringFunctions\arm_conv_partial_fast_q31.c \DSP\Source\FilteringFunctions\arm_conv_partial_opt_q15.c \DSP\Source\FilteringFunctions\arm_conv_partial_opt_q7.c \DSP\Source\FilteringFunctions\arm_conv_partial_q15.c \DSP\Source\FilteringFunctions\arm_conv_partial_q31.c \DSP\Source\FilteringFunctions\arm_conv_partial_q7.c \DSP\Source\FilteringFunctions\arm_conv_q15.c \DSP\Source\FilteringFunctions\arm_conv_q31.c \DSP\Source\FilteringFunctions\arm_conv_q7.c \DSP\Source\FilteringFunctions\arm_correlate_f32.c \DSP\Source\FilteringFunctions\arm_correlate_fast_opt_q15.c \DSP\Source\FilteringFunctions\arm_correlate_fast_q15.c \DSP\Source\FilteringFunctions\arm_correlate_fast_q31.c \DSP\Source\FilteringFunctions\arm_correlate_opt_q15.c \DSP\Source\FilteringFunctions\arm_correlate_opt_q7.c \DSP\Source\FilteringFunctions\arm_correlate_q15.c \DSP\Source\FilteringFunctions\arm_correlate_q31.c \DSP\Source\FilteringFunctions\arm_correlate_q7.c \DSP\Source\FilteringFunctions\arm_fir_decimate_f32.c \DSP\Source\FilteringFunctions\arm_fir_decimate_fast_q15.c \DSP\Source\FilteringFunctions\arm_fir_decimate_fast_q31.c \DSP\Source\FilteringFunctions\arm_fir_decimate_init_f32.c \DSP\Source\FilteringFunctions\arm_fir_decimate_init_q15.c \DSP\Source\FilteringFunctions\arm_fir_decimate_init_q31.c \DSP\Source\FilteringFunctions\arm_fir_decimate_q15.c \DSP\Source\FilteringFunctions\arm_fir_decimate_q31.c \DSP\Source\FilteringFunctions\arm_fir_f32.c \DSP\Source\FilteringFunctions\arm_fir_fast_q15.c \DSP\Source\FilteringFunctions\arm_fir_fast_q31.c \DSP\Source\FilteringFunctions\arm_fir_interpolate_f32.c \DSP\Source\FilteringFunctions\arm_fir_interpolate_init_f32.c \DSP\Source\FilteringFunctions\arm_fir_interpolate_init_q15.c \DSP\Source\FilteringFunctions\arm_fir_interpolate_init_q31.c \DSP\Source\FilteringFunctions\arm_fir_interpolate_q15.c \DSP\Source\FilteringFunctions\arm_fir_interpolate_q31.c \DSP\Source\FilteringFunctions\arm_fir_lattice_f32.c \DSP\Source\FilteringFunctions\arm_fir_lattice_q15.c \DSP\Source\FilteringFunctions\arm_fir_lattice_q31.c \DSP\Source\FilteringFunctions\arm_fir_q15.c \DSP\Source\FilteringFunctions\arm_fir_q31.c \DSP\Source\FilteringFunctions\arm_fir_q7.c \DSP\Source\FilteringFunctions\arm_fir_sparse_f32.c \DSP\Source\FilteringFunctions\arm_fir_sparse_init_f32.c \DSP\Source\FilteringFunctions\arm_fir_sparse_init_q15.c \DSP\Source\FilteringFunctions\arm_fir_sparse_init_q31.c \DSP\Source\FilteringFunctions\arm_fir_sparse_init_q7.c \DSP\Source\FilteringFunctions\arm_fir_sparse_q15.c \DSP\Source\FilteringFunctions\arm_fir_sparse_q31.c \DSP\Source\FilteringFunctions\arm_fir_sparse_q7.c \DSP\Source\FilteringFunctions\arm_iir_lattice_f32.c \DSP\Source\FilteringFunctions\arm_iir_lattice_q15.c \DSP\Source\FilteringFunctions\arm_iir_lattice_q31.c \DSP\Source\FilteringFunctions\arm_lms_f32.c \DSP\Source\FilteringFunctions\arm_lms_norm_f32.c \DSP\Source\FilteringFunctions\arm_lms_norm_q15.c \DSP\Source\FilteringFunctions\arm_lms_norm_q31.c \DSP\Source\FilteringFunctions\arm_lms_q15.c \DSP\Source\FilteringFunctions\arm_lms_q31.c \DSP\Source\MatrixFunctions\arm_mat_add_f32.c \DSP\Source\MatrixFunctions\arm_mat_add_q15.c \DSP\Source\MatrixFunctions\arm_mat_add_q31.c \DSP\Source\MatrixFunctions\arm_mat_cmplx_mult_f32.c \DSP\Source\MatrixFunctions\arm_mat_cmplx_mult_q15.c \DSP\Source\MatrixFunctions\arm_mat_cmplx_mult_q31.c \DSP\Source\MatrixFunctions\arm_mat_inverse_f32.c \DSP\Source\MatrixFunctions\arm_mat_inverse_f64.c \DSP\Source\MatrixFunctions\arm_mat_mult_f32.c \DSP\Source\MatrixFunctions\arm_mat_mult_fast_q15.c \DSP\Source\MatrixFunctions\arm_mat_mult_fast_q31.c \DSP\Source\MatrixFunctions\arm_mat_mult_q15.c \DSP\Source\MatrixFunctions\arm_mat_mult_q31.c \DSP\Source\MatrixFunctions\arm_mat_scale_f32.c \DSP\Source\MatrixFunctions\arm_mat_scale_q15.c \DSP\Source\MatrixFunctions\arm_mat_scale_q31.c \DSP\Source\MatrixFunctions\arm_mat_sub_f32.c \DSP\Source\MatrixFunctions\arm_mat_sub_q15.c \DSP\Source\MatrixFunctions\arm_mat_sub_q31.c \DSP\Source\MatrixFunctions\arm_mat_trans_f32.c \DSP\Source\MatrixFunctions\arm_mat_trans_q15.c \DSP\Source\MatrixFunctions\arm_mat_trans_q31.c \DSP\Source\StatisticsFunctions\arm_max_f32.c \DSP\Source\StatisticsFunctions\arm_max_q15.c \DSP\Source\StatisticsFunctions\arm_max_q31.c \DSP\Source\StatisticsFunctions\arm_max_q7.c \DSP\Source\StatisticsFunctions\arm_mean_f32.c \DSP\Source\StatisticsFunctions\arm_mean_q15.c \DSP\Source\StatisticsFunctions\arm_mean_q31.c \DSP\Source\StatisticsFunctions\arm_mean_q7.c \DSP\Source\StatisticsFunctions\arm_min_f32.c \DSP\Source\StatisticsFunctions\arm_min_q15.c \DSP\Source\StatisticsFunctions\arm_min_q31.c \DSP\Source\StatisticsFunctions\arm_min_q7.c \DSP\Source\StatisticsFunctions\arm_power_f32.c \DSP\Source\StatisticsFunctions\arm_power_q15.c \DSP\Source\StatisticsFunctions\arm_power_q31.c \DSP\Source\StatisticsFunctions\arm_power_q7.c \DSP\Source\StatisticsFunctions\arm_rms_f32.c \DSP\Source\StatisticsFunctions\arm_rms_q15.c \DSP\Source\StatisticsFunctions\arm_rms_q31.c \DSP\Source\StatisticsFunctions\arm_std_f32.c \DSP\Source\StatisticsFunctions\arm_std_q15.c \DSP\Source\StatisticsFunctions\arm_std_q31.c \DSP\Source\StatisticsFunctions\arm_var_f32.c \DSP\Source\StatisticsFunctions\arm_var_q15.c \DSP\Source\StatisticsFunctions\arm_var_q31.c \DSP\Source\SupportFunctions\arm_copy_f32.c \DSP\Source\SupportFunctions\arm_copy_q15.c \DSP\Source\SupportFunctions\arm_copy_q31.c \DSP\Source\SupportFunctions\arm_copy_q7.c \DSP\Source\SupportFunctions\arm_fill_f32.c \DSP\Source\SupportFunctions\arm_fill_q15.c \DSP\Source\SupportFunctions\arm_fill_q31.c \DSP\Source\SupportFunctions\arm_fill_q7.c \DSP\Source\SupportFunctions\arm_float_to_q15.c \DSP\Source\SupportFunctions\arm_float_to_q31.c \DSP\Source\SupportFunctions\arm_float_to_q7.c \DSP\Source\SupportFunctions\arm_q15_to_float.c \DSP\Source\SupportFunctions\arm_q15_to_q31.c \DSP\Source\SupportFunctions\arm_q15_to_q7.c \DSP\Source\SupportFunctions\arm_q31_to_float.c \DSP\Source\SupportFunctions\arm_q31_to_q15.c \DSP\Source\SupportFunctions\arm_q31_to_q7.c \DSP\Source\SupportFunctions\arm_q7_to_float.c \DSP\Source\SupportFunctions\arm_q7_to_q15.c \DSP\Source\SupportFunctions\arm_q7_to_q31.c \DSP\Source\TransformFunctions\arm_bitreversal.c \DSP\Source\TransformFunctions\arm_cfft_radix4_f32.c \DSP\Source\TransformFunctions\arm_cfft_radix4_q15.c \DSP\Source\TransformFunctions\arm_cfft_radix4_q31.c \DSP\Source\TransformFunctions\arm_dct4_f32.c \DSP\Source\TransformFunctions\arm_dct4_init_f32.c \DSP\Source\TransformFunctions\arm_dct4_init_q15.c \DSP\Source\TransformFunctions\arm_dct4_q15.c \DSP\Source\TransformFunctions\arm_dct4_q31.c \DSP\Source\TransformFunctions\arm_rfft_f32.c \DSP\Source\TransformFunctions\arm_rfft_fast_f32.c \DSP\Source\TransformFunctions\arm_rfft_init_f32.c \DSP\Source\TransformFunctions\arm_rfft_q15.c \DSP\Source\TransformFunctions\arm_rfft_q31.c \Pack\Example\Boards\Keil\MCB1800\Blinky\RTE\Device\LPC1857\system_LPC18xx.c \Pack\Example\Boards\Keil\MCB1800\Blinky_ULp\RTE\Device\LPC1857\system_LPC18xx.c \Pack\Example\Boards\Keil\MCB1800\Common\Audio_UDA1380.c \Pack\Example\Boards\Keil\MCB1800\Common\Touch_STMPE811.c \Pack\Example\Boards\Keil\MCB1800\RTX_Blinky\RTE\Device\LPC1857\system_LPC18xx.c \Pack\Example\CMSIS_Driver\EMAC_LPC18xx.c Device\ARM\ARMCM0\Source\GCC\startup_ARMCM0.c Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.c Device\ARM\ARMCM23\Source\GCC\startup_ARMCM23.c Device\ARM\ARMCM33\Source\GCC\startup_ARMCM33.c Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c Device\ARM\ARMCM7\Source\GCC\startup_ARMCM7.c Device\ARM\ARMSC000\Source\GCC\startup_ARMSC000.c Device\ARM\ARMSC300\Source\GCC\startup_ARMSC300.c Device\ARM\ARMv8MBL\Source\GCC\startup_ARMv8MBL.c Device\ARM\ARMv8MML\Source\GCC\startup_ARMv8MML.c

Please fix this soon Reto Felix

[JonatanAntoni]

Hi @CanastraRF,

Thank you for making us aware of this inconsistency. I have converted all suffixes to uppercase now.

May I ask you to double check if your MISRA checker is now satisfied? Please close the issue if so.

Cheers, Jonatan

[CanastraRF]

Hi Jonatan, Thank you for Fixing this issue in most places. But PcLint reports the following issues:

if (data == 0u) { return 32u; } cmsis_compiler.h(138): Note 1960: Violates MISRA C++ 2008 Required Rule 2-13-4, Lower case literal suffix: u

count += 1u; cmsis_compiler.h(145): Note 1960: Violates MISRA C++ 2008 Required Rule 2-13-4, Lower case literal suffix: u

mask = mask >> 1u; cmsis_compiler.h(146): Note 1960: Violates MISRA C++ 2008 Required Rule 2-13-4, Lower case literal suffix: u

uint32_t mask = 0x80000000; cmsis_compiler.h(141): Note 1960: Violates MISRA C++ 2008 Required Rule 2-13-3, Unsigned octal and hexadecimal literals require a 'U' suffix cmsis_compiler.h(141): Note 9105: unsigned octal and hexadecimal literals require a 'U' suffix [MISRA C++ Rule 2-13-3]

while ((data & mask) == 0) cmsis_compiler.h(143): note 9029: an unsigned value and a signed value cannot be used together as operands to == [MISRA 2012 Rule 10.4, required] cmsis_compiler.h(143): Note 1960: Violates MISRA C++ 2008 Required Rule 5-0-4, Implicit conversion changes signedness

mpu_armv7.h(118): Note 1917: empty prototype for definition, assumed '(void)'

mpu_armv8.h(59) #define ARM_MPU_ATTR(O, I) (((O & 0xFu) << 4U) | (((O & 0xFu) != 0U) ? (I & 0xFu) : ((I & 0x3U) << 2U)))

mpu_armv8.h(168) const uint32_t mask = 0xFFu << pos;

Please fix them too. Reto Felix

[JonatanAntoni]

Hi @CanastraRF,

Thanks for double checking. I have looked over those. The latest commit should fix them as well.

Cheers, Jonatan

[CanastraRF]

Hi Jonatan Thanks again. Now it complain better to misra Reto