Open namniav opened 5 days ago
Describe the bug
From https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-widen, each neon vector shift left and widen intrinsic has a variant with n == bit width.
n == bit width
Both link to the same developer.arm.com page for vshll_n_s8 and the documented argument preparation there is n -> minimum: 0; maximum: 7.
vshll_n_s8
n -> minimum: 0; maximum: 7
What is the use of the second variant? Or is it a mistake?
Thanks for the bug report.
This is indeed a bug. [developer.arm.com]() is missing the second variant, which is translated into the SHLL instruction (instead of SSHLL).
SHLL
SSHLL
Describe the bug
From https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-widen, each neon vector shift left and widen intrinsic has a variant with
n == bit width
.Both link to the same developer.arm.com page for
vshll_n_s8
and the documented argument preparation there isn -> minimum: 0; maximum: 7
.What is the use of the second variant? Or is it a mistake?