The PE test 10 uses the PM (Performance Monitors) counter to check the PMU Overflow signal. However, if the PM Counter hasn't been enabled by firmware (the corresponding bits in PMCNTENSET_EL0 register haven't been set), the counter won't work and generate the interrupt, which will fail the PE test 10.
Therefore, the test case may need to enable the PM counter before generating the interrupt. If the PM counter should be enabled by firmware, the test case should be updated to print out some messages saying that this is a firmware issue (PMCNTENSET_EL0 need to be set) rather than a hardware issue that the interrupt hasn't been generated.
The PE test 10 uses the PM (Performance Monitors) counter to check the PMU Overflow signal. However, if the PM Counter hasn't been enabled by firmware (the corresponding bits in PMCNTENSET_EL0 register haven't been set), the counter won't work and generate the interrupt, which will fail the PE test 10. Therefore, the test case may need to enable the PM counter before generating the interrupt. If the PM counter should be enabled by firmware, the test case should be updated to print out some messages saying that this is a firmware issue (PMCNTENSET_EL0 need to be set) rather than a hardware issue that the interrupt hasn't been generated.
https://developer.arm.com/documentation/ddi0601/2023-12/AArch64-Registers/PMCNTENSET-EL0--Performance-Monitors-Count-Enable-Set-Register