Closed hrw closed 2 weeks ago
QEMU 'max' cpu implements FEAT_EBF16 (output of my ArmCpuInfo tool):
ISAR1 | LS64 | 63:60 | 0000 | FEAT_LS64 not implemented. ISAR1 | XS | 59:56 | 0000 | FEAT_XS not implemented. ISAR1 | I8MM | 55:52 | 0001 | FEAT_I8MM implemented. ISAR1 | DGH | 51:48 | 0001 | FEAT_DGH implemented. ISAR1 | BF16 | 47:44 | 0010 | FEAT_EBF16 implemented. ISAR1 | SPECRES | 43:40 | 0001 | FEAT_SPECRES implemented. ISAR1 | SB | 39:36 | 0001 | FEAT_SB implemented. ISAR1 | FRINTTS | 35:32 | 0001 | FEAT_FRINTTS implemented. ISAR1 | GPI | 31:28 | 0000 | FEAT_PACIMP not implemented. ISAR1 | GPA | 27:24 | 0001 | FEAT_PACQARMA5 implemented. ISAR1 | LRCPC | 23:20 | 0010 | FEAT_LRCPC2 implemented. ISAR1 | FCMA | 19:16 | 0001 | FEAT_FCMA implemented. ISAR1 | JSCVT | 15:12 | 0001 | FEAT_JSCVT implemented. ISAR1 | API | 11:8 | 0000 | Address Authentication (API) not implemented. ISAR1 | APA | 7:4 | 0101 | FEAT_FPACCOMBINE implemented. | | | | FEAT_PACQARMA5 implemented. ISAR1 | DPB | 3:0 | 0010 | FEAT_DPB2 implemented.
But test 32 checks only for BF16:
/* ID_AA64ISAR1_EL1.BF16[47:44] = 0b0001 indicate FEAT_BF16 support */ data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 44, 47); if (data == 1) val_set_status(index, RESULT_PASS(TEST_NUM, 01)); else val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
ops, that's in sbsa-acs ;(
Filled as https://github.com/ARM-software/sbsa-acs/issues/476
QEMU 'max' cpu implements FEAT_EBF16 (output of my ArmCpuInfo tool):
But test 32 checks only for BF16: