ARM-software / ebbr

Embedded Base Boot Requirements Specification
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Wrong link to hypervisor extension for RISC-V #100

Closed xypron closed 1 year ago

xypron commented 1 year ago

2.3.2 RISC-V Privilege Levels

The Hypervisor ISA 1.0 is ratified and described in The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203 https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf

Chapter 8.1 "Privilege Modes" of that specification describes the available privilege levels for systems with Hypervisor extension.

The following sentence is obviously wrong in the EBBR and needs to be updated:

"Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC] is still in draft state."