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ARM-software / tf-issues

Issue tracking for the ARM Trusted Firmware project
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Both the BL2 and BL32 set up the S-EL1 MMU, is it reasonable? #115

Closed kelvinklee closed 10 years ago

kelvinklee commented 10 years ago

Both the BL2 and BL32 will run in the S-EL1 and both of them will configure the MMU while initialising.

After the BL2 completes, the control right will be given to BL31 via the BL1's exception handler. If there is a BL32, the BL31 will boot the BL32 firstly before going to BL33.

I think it had better tear down the MMU setting at the end of the BL2.

athoelke commented 10 years ago

BL3-1 currently enters BL3-2 with only a basic processor state set up, at least this is the case for the TSP. In particular SCTLR_EL1 has the M, C and I bits clear so that translation is not enabled at the BL3-2 entrypoint.

This is sub-optimal from a performance perspective as BL3-2 must then initialise translation tables and MMU configuration before being able to enable the MMU and data caches.

To be able to run with caches enabled from entry, BL2 and BL3-1 would need to set up appropriate translation tables (possibly temporary ones) for BL3-2 and set the EL1 translation registers prior to entering BL3-2 at EL1. We may consider providing an example of this in future with the TSPD and TSP.

danh-arm commented 10 years ago

I believe the question is answered. Please re-open if you disagree.