Closed mahamble closed 10 years ago
I believe this is already tracked by https://github.com/ARM-software/tf-issues/issues/24
Ok, thanks. Do you know if it will be fixed in the coming 0.3 release?
It's not in the current set of in-flight patches but we can prioritize this straight after the release if it's hurting you.
Yes please...
Looks like common code in bl1 and bl31 access the platform specific system counter registers:
https://github.com/ARM-software/arm-trusted-firmware/blob/master/bl1/aarch64/bl1_arch_setup.c#L65
bl1/aarch64/bl1_arch_setup.c:
counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
https://github.com/ARM-software/arm-trusted-firmware/blob/master/bl31/aarch64/bl31_arch_setup.c#L66
bl31/aarch64/bl31_arch_setup.c:
counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
Looking at the A53 TRM the system counter interface (which I believe this code is accessing) is SOC specific so this interface should be moved to the platform?