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ASU-VDA-Lab
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2024_ICCAD_Contest_Gate_Sizing_Benchmark
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different code in branch -cad-contest-test
#13
weiii1121
opened
2 hours ago
0
Submission question
#12
steveniscoming
opened
7 hours ago
0
'Timing' object has no attribute 'resetTiming'
#11
steveniscoming
closed
1 day ago
4
Can we perform gate sizing on Macro or not?
#10
steveniscoming
closed
2 days ago
2
Change the OpenROAD submodule to point to my own fork that fix the eq…
#9
bingyuew
closed
5 days ago
0
Pin-pin edge doesn’t contain the timing arc delay
#8
cyilu
closed
3 days ago
1
update methods to get the equivcells
#7
bingyuew
closed
1 week ago
1
OpenROAD_example.py can't be valid for new Benchmark
#6
steveniscoming
closed
1 week ago
2
Benchmark reference sizing results difference
#5
Akilax0
opened
1 week ago
21
bug in evalutaion.py
#4
cai-zhi-jie
closed
1 week ago
1
'Timing' object has no attribute 'getMaxSlewLimit'
#3
Yufan-Du
closed
5 days ago
3
No attribute error for Timing,makeEquivCells in openroad python API
#2
Akilax0
closed
3 weeks ago
1
Dockerfile issue
#1
IfedayoVLSI
closed
5 days ago
4