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AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells
Apache License 2.0
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Add support for 1R1W regfiles #180

Open xobs opened 1 year ago

xobs commented 1 year ago

DFFRAM currently supports 1RW2R regfiles, which is common on many architectures including RISC-V. However, some architectures only support reading from one operand. For example, RISC-V compressed instructions only support accessing one source and one destination operand.

Currently, routing pressure on GF180MCU is very high, meaning a lot of extra halo needs to be added for the wiring. It's possible to synthesize a 1RW1R memory, but even that has extra read circuitry on the write path that is unnecessary.

It would be nice to be able to shrink the regfile such that it generates a 1W1R block.

mohamedleithy commented 1 year ago

Will start working on this. Stay tuned