AUCOHL / Lighter

An automatic clock gating utility
Apache License 2.0
42 stars 5 forks source link

Move module to be part of yosys-f4pga-plugins #9

Closed mithro closed 1 year ago

mithro commented 2 years ago

Rather than having yet another repository which needs to be installed along with Yosys, it would be better to have this be part of the yosys-f4pga-plugins repository which contains other useful plugins like SystemVerilog support (using UHDM), SDC support, and design inspection.

This means you'll then get the benefit of being part of a bigger suite of plugins, including people to review your code, etc.

mithro commented 2 years ago

FYI - I logged https://github.com/chipsalliance/yosys-f4pga-plugins/issues/312 about the fact having f4pga in the name is a little confusing as many of the plugins are non-FPGA specific.

shalan commented 2 years ago

Makes sense.

kanndil commented 1 year ago

I created this pull request https://github.com/chipsalliance/yosys-f4pga-plugins/pull/382 to the yosys-f4pga-plugins repository, and it is pending a review.

mithro commented 1 year ago

FYI - @kgugala / @mgielda

kanndil commented 1 year ago

The pull request https://github.com/chipsalliance/yosys-f4pga-plugins/pull/382 is merged in https://github.com/chipsalliance/yosys-f4pga-plugins/commit/a20c6a96d9fd4b8989940a6608501784e02e78b1