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Abhiyanta-Community / Hardware-and-Timer-Interrupt-with-ATmega328p-Hardware

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Getting started with Timers #5

Closed PRITVARMORA closed 2 years ago

PRITVARMORA commented 2 years ago

Understand the Timers specifications of ATmega328P (preferred source Datasheet). List out the register which needs to be configured while using a Timer.

vasoyasujal42 commented 2 years ago

In this task we need to refer data sheet for this we only focus on this portions.

  1. 8-bit Timer/Counter0 with PWM
  2. Timer/Counter0 and Timer/Counter1 Prescalers
vasoyasujal42 commented 2 years ago

==>Conclusion

-->I this task we refer the data sheet for timer interrupt in data sheet we refer the 16 bit and 8 bit timer like timer0, timer1 and timer2 timer0 and timer2 has 8 bit type of timers and timer1 has 16 bit timer and timers have also special functions but basic function are output compare match and input capture.
-->In timer TCNT1 for accessing timer/counter1 value and same for timer0 and timer2. -->timer 0 and 2 are 8 bits meaning it could count from 0 to 255. Timer 1 on the other hand, is 16 bits so it could count from 0 to 65546. Once a timer reaches its maximum value, it will go back to 0 or start decreasing depending on the selected mode. So basically it would create a zig zag curve. The timer starts increasing its value from 0. When we reach 255 in case of the 8 bits register, we go back to 0 and increase once again. This will create a triangle shape curve and we could use this to create our interruptions. -->The prescalar divides the number of pulses from the system clock by the number you define which could be 8, 64, 256 and so on, and later we will see how to define this prescalar division number. the prescalar has control by TCCR1B (timer/counter control register B). TCCR1B has a set bit for prescalar CS12, CS11 and CS10. CS12 | CS11 | CS10 0 0 1 - CLOCK/1 0 1 0 - CLOCK/8 0 1 1 - CLOCK/64 1 0 0 - CLOCK/256 1 0 1 - CLOCK/1024 -->In output compare match 16 bit comparator continuously compares TCNT1 with the output compare register(OCR1A). If TCNT1 equal OCR1A the compare signals a match. A match will set the output compare flag (OCF1A) at the net timer clock cycle. -->OCR1A (Output Compare Register 1 A ) and OCR1B (Output Compare Register 1 A) This register use for the store the vale for output compare match. -->TIMSK1 (Timer/Counter1 Interrupt Mask Register) This register use for which type of functions we want to use like Comparer Match Interrupt Enable or Overflow Interrupt Enable or Input Capture Interrupt Enable or Reserved Bit Enable.