Incorrect 3-level arch in the exercise

[leizhaocs]

Hi, I am going through the exercises in the 2020_ispass tutorial, however I am confused on the 3-level architecture, it seems the yaml file defines a 2-level arch instead of a 3-level arch. For example, below is the definition in the exercise 04-model-conv1d+oc-3levelspation:

architecture:
  version: 0.4
  nodes:
  - !Container
    name: System
    attributes:
      technology: "40nm"
      global_cycle_seconds: 1e-9

  - !Component
    name: MainMemory
    class: DRAM
    attributes:
      width: 256
      datawidth: 8

  - !Container
    name: PE
    spatial: {meshX: 16}

  - !Component
    name: GlobalBuffer
    class: SRAM
    attributes:
      depth: 32768
      width: 64
      datawidth: 8

  - !Component
    name: RegisterFile
    class: regfile
    attributes:
      depth: 64
      width: 8
      datawidth: 8

  - !Component
    name: MACC
    class: intmac
    attributes:
      width: 8

If my understand is correct, the GlobalBuffer is defined insided the PE instead of shared by all PEs. From the flattened architecture output, the GlobalBuffer is indeed instantiated 16 times. Below is what I think the correct arch file:

architecture:
  version: 0.4
  nodes:
  - !Container
    name: System
    attributes:
      technology: "40nm"
      global_cycle_seconds: 1e-9

  - !Component
    name: MainMemory
    class: DRAM
    attributes:
      width: 256
      datawidth: 8

  - !Container
    name: chip

  - !Component
    name: GlobalBuffer
    class: SRAM
    attributes:
      depth: 32768
      width: 64
      datawidth: 8

  - !Container
    name: PE
    spatial: {meshX: 16}

  - !Component
    name: RegisterFile
    class: regfile
    attributes:
      depth: 64
      width: 8
      datawidth: 8

  - !Component
    name: MACC
    class: intmac
    attributes:
      width: 8