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AdDraw / buffer_size_est

Simple TB and equation in order to estimate buffer size required to not overfill it
MIT License
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Optimizations #7

Open AdDraw opened 1 year ago

AdDraw commented 1 year ago

Optimizations that can be done:

  1. cocotb optimizations
    • [x] move clock generation to HDL
  2. TO BE ADDED
AdDraw commented 1 year ago

HDL Clock generation commit 4ae21a31cea04c92b6600ea422fb8439ecd1cde4:

pre_opt:

-----------------------------------
-- Testbench check in progress... -
-----------------------------------
['make', 'WRITE_BURST_SIZE=1024', 'WRITE_IDLE_CYCLES_BETWEEN_BURSTS=1', 'WRITE_NUMBER_OF_BURSTS=100', 'READ_BURST_SIZE=10', 'READ_IDLE_CYCLES_BETWEEN_BURSTS=1', 'FIFO_DEPTH_W=14', 'MIN_FIFO_SIZE=9220', 'WRITE_FREQ=1', 'READ_FREQ=1']
stdout: /home/adam/git_repos/buffer_fill_eq/submodules/verinoc/srcs/components/circ_fifo.v /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_Ndeep.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/synchronizer_2ff.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/gray2bin.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/bin2gray.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_2deep.sv tb_top.v

COMPILE_ARGS = -P tb_top.WRITE_BURST_SIZE=1024 -P tb_top.WRITE_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.WRITE_NUMBER_OF_BURSTS=100 -P tb_top.READ_BURST_SIZE=10 -P tb_top.READ_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.FIFO_DEPTH_W=14 -P tb_top.MIN_FIFO_SIZE=9220 -P tb_top.WRITE_FREQ=1 -P tb_top.READ_FREQ=1 -f sim_build/cmds.f -g2012 

 Starting SIMULATION on sob, 3 cze 2023, 19:32:37 CEST

rm -f results.xml
make -f Makefile results.xml
make[1]: Entering directory '/home/adam/git_repos/buffer_fill_eq/buffer_throghput_tb'
mkdir -p sim_build
/usr/local/bin/iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s tb_top -P tb_top.WRITE_BURST_SIZE=1024 -P tb_top.WRITE_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.WRITE_NUMBER_OF_BURSTS=100 -P tb_top.READ_BURST_SIZE=10 -P tb_top.READ_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.FIFO_DEPTH_W=14 -P tb_top.MIN_FIFO_SIZE=9220 -P tb_top.WRITE_FREQ=1 -P tb_top.READ_FREQ=1 -f sim_build/cmds.f -g2012   /home/adam/git_repos/buffer_fill_eq/submodules/verinoc/srcs/components/circ_fifo.v                /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_Ndeep.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/synchronizer_2ff.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/gray2bin.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/bin2gray.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_2deep.sv  tb_top.v
rm -f results.xml
MODULE=test TESTCASE= TOPLEVEL=tb_top TOPLEVEL_LANG=verilog \
         /usr/local/bin/vvp -M /home/adam/.local/lib/python3.10/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp 
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
     0.00ns INFO     cocotb                             Running on Icarus Verilog version 11.0 (stable)
     0.00ns INFO     cocotb                             Running tests with cocotb v1.7.1 from /home/adam/.local/lib/python3.10/site-packages/cocotb
     0.00ns INFO     cocotb                             Seeding Python random module with 1685813558
     0.00ns INFO     cocotb.regression                  Found test test.test
     0.00ns INFO     cocotb.regression                  running test (1/1)
     0.00ns INFO     cocotb                             Write Freq: 1Hz Period: 1000000000.0ns
     0.00ns INFO     cocotb                             Read Freq: 1Hz Period: 1000000000.0ns
102509500000000.00ns INFO     cocotb.regression                  test passed
102509500000000.00ns INFO     cocotb.regression                  **************************************************************************************
                                                                 ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
                                                                 **************************************************************************************
                                                                 ** test.test                      PASS   102509500000000.00          42.19   2429947249026.45  **
                                                                 **************************************************************************************
                                                                 ** TESTS=1 PASS=1 FAIL=0 SKIP=0          102509500000000.00          42.53   2410474997536.86  **
                                                                 **************************************************************************************

VCD info: dumpfile dump.vcd opened for output.
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
VCD warning: ignoring signals in previously scanned scope tb_top.genblk1.fifo_inst.
make[1]: Leaving directory '/home/adam/git_repos/buffer_fill_eq/buffer_throghput_tb'

stderr: None
return_code: 0

post_opt:

-----------------------------------
-- Testbench check in progress... -
-----------------------------------
WP: 500000000.0
RP: 500000000.0
['make', 'WRITE_BURST_SIZE=1024', 'WRITE_IDLE_CYCLES_BETWEEN_BURSTS=1', 'WRITE_NUMBER_OF_BURSTS=100', 'READ_BURST_SIZE=10', 'READ_IDLE_CYCLES_BETWEEN_BURSTS=1', 'FIFO_DEPTH_W=14', 'MIN_FIFO_SIZE=9220', 'WRITE_FREQ=1', 'READ_FREQ=1', 'WRITE_PERIOD_HALF=500000000.0', 'READ_PERIOD_HALF=500000000.0']
stdout: /home/adam/git_repos/buffer_fill_eq/submodules/verinoc/srcs/components/circ_fifo.v /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_Ndeep.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/synchronizer_2ff.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/gray2bin.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/bin2gray.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_2deep.sv tb_top.v

COMPILE_ARGS = -P tb_top.WRITE_BURST_SIZE=1024 -P tb_top.WRITE_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.WRITE_NUMBER_OF_BURSTS=100 -P tb_top.READ_BURST_SIZE=10 -P tb_top.READ_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.FIFO_DEPTH_W=14 -P tb_top.MIN_FIFO_SIZE=9220 -P tb_top.WRITE_FREQ=1 -P tb_top.READ_FREQ=1 -P tb_top.WRITE_PERIOD_HALF=500000000.0 -P tb_top.READ_PERIOD_HALF=500000000.0 -f sim_build/cmds.f -g2012 

 Starting SIMULATION on sob, 3 cze 2023, 19:34:22 CEST

rm -f results.xml
make -f Makefile results.xml
make[1]: Entering directory '/home/adam/git_repos/buffer_fill_eq/buffer_throghput_tb'
mkdir -p sim_build
/usr/local/bin/iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s tb_top -P tb_top.WRITE_BURST_SIZE=1024 -P tb_top.WRITE_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.WRITE_NUMBER_OF_BURSTS=100 -P tb_top.READ_BURST_SIZE=10 -P tb_top.READ_IDLE_CYCLES_BETWEEN_BURSTS=1 -P tb_top.FIFO_DEPTH_W=14 -P tb_top.MIN_FIFO_SIZE=9220 -P tb_top.WRITE_FREQ=1 -P tb_top.READ_FREQ=1 -P tb_top.WRITE_PERIOD_HALF=500000000.0 -P tb_top.READ_PERIOD_HALF=500000000.0 -f sim_build/cmds.f -g2012   /home/adam/git_repos/buffer_fill_eq/submodules/verinoc/srcs/components/circ_fifo.v           /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_Ndeep.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/synchronizer_2ff.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/gray2bin.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/bin2gray.sv /home/adam/git_repos/buffer_fill_eq/submodules/cdc/src/async_fifo_2deep.sv  tb_top.v
rm -f results.xml
MODULE=test TESTCASE= TOPLEVEL=tb_top TOPLEVEL_LANG=verilog \
         /usr/local/bin/vvp -M /home/adam/.local/lib/python3.10/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp 
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
     0.00ns INFO     cocotb                             Running on Icarus Verilog version 11.0 (stable)
     0.00ns INFO     cocotb                             Running tests with cocotb v1.7.1 from /home/adam/.local/lib/python3.10/site-packages/cocotb
     0.00ns INFO     cocotb                             Seeding Python random module with 1685813663
     0.00ns INFO     cocotb.regression                  Found test test.test
     0.00ns INFO     cocotb.regression                  running test (1/1)
     0.00ns INFO     cocotb                             Write Freq: 1Hz Period: 1000000000.0ns
     0.00ns INFO     cocotb                             Read Freq: 1Hz Period: 1000000000.0ns
102509500000000.00ns INFO     cocotb.regression                  test passed
102509500000000.00ns INFO     cocotb.regression                  **************************************************************************************
                                                                 ** TEST                          STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
                                                                 **************************************************************************************
                                                                 ** test.test                      PASS   102509500000000.00          19.71   5200158694701.12  **
                                                                 **************************************************************************************
                                                                 ** TESTS=1 PASS=1 FAIL=0 SKIP=0          102509500000000.00          20.07   5108577418568.70  **
                                                                 **************************************************************************************

VCD info: dumpfile dump.vcd opened for output.
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
VCD warning: ignoring signals in previously scanned scope tb_top.genblk1.fifo_inst.
make[1]: Leaving directory '/home/adam/git_repos/buffer_fill_eq/buffer_throghput_tb'

stderr: None
return_code: 0