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AdDraw / veriNoC

Master Thesis 2020/2022 Network on Chip
https://addraw.github.io/veriNoC/
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Advanced Synthesis #17

Closed AdDraw closed 3 years ago

AdDraw commented 3 years ago
  1. Ask promoter for the stdlib that I need to synth the design to.
  2. Synth with this and pass POST-SYNTH sim
  3. Any other requirements ?

stdlib should be placed in the repo

AdDraw commented 3 years ago

used cmos_cells.lib provided in YOSYS but not used by default.

Contains:

Placed in synth/cmos_cells.v