Allow for easy customization of a NoC

AdDraw / veriNoC

Master Thesis 2020/2022 Network on Chip

https://addraw.github.io/veriNoC/

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Open AdDraw opened 2 years ago

AdDraw commented 2 years ago

Ideally I should be able to configure a NoC without a lot of manual signal mappings etc.

This seems like a far of dream but might be possible through either:

SystemVerilog
Using HLS / New HDLs (Chisel, nmigen(https://github.com/amaranth-lang), SpinaHDL)