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AdamVerner / oscilo

school project
GNU General Public License v3.0
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add sources to documentation #5

Closed AdamVerner closed 5 years ago

AdamVerner commented 6 years ago

write used modules into comments

AdamVerner commented 6 years ago

RAM from http://www.asic-world.com/examples/systemverilog/ram_sp_ar_sw.html#Single_Port_RAM_Asynch_Read,_Synch_Write

AdamVerner commented 5 years ago

the ram wasn't working, I had to make my own.

the rest I did all by myself and StackExchange too, so this issue is not relevant.